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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 09:45:19 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:27:52 +0000 |
| commit | 2fb6f68ef09358aa6f2550519e71a1d74702d5ef (patch) | |
| tree | 68e32aec7db7d4d2bc6329691ad44f72d14d1244 /src/mainboard/lenovo/x200 | |
| parent | ea6a3b488c238f9b79ee3aeaedaf6b06e2dc4023 (diff) | |
nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/x200')
| -rw-r--r-- | src/mainboard/lenovo/x200/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 059dc005cb..dc059f0d50 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,6 +9,7 @@ chip northbridge/intel/gm45 register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms device cpu_cluster 0 on + ops gm45_cpu_bus_ops chip cpu/intel/socket_BGA956 device lapic 0 on end end @@ -28,6 +29,7 @@ chip northbridge/intel/gm45 register "pci_mmio_size" = "2048" device domain 0 on + ops gm45_pci_domain_ops device pci 00.0 on subsystemid 0x17aa 0x20e0 end # host bridge |