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| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-22 04:31:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-06 10:48:46 +0000 |
| commit | 7b2b57b0b8ae451f80b97582cc6c86004aaab471 (patch) | |
| tree | 51e0358849a5d81da6d9f74b31e1c688feed3630 /src/mainboard/lenovo/thinkcentre_m710s | |
| parent | 71814b0e5bedd01e6258afb26da72e28a49e0aae (diff) | |
soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/thinkcentre_m710s')
0 files changed, 0 insertions, 0 deletions