diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-15 18:26:05 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:40:16 +0000 |
commit | a1e46aea79a7d51e006d91b9a6433a91ae6745d3 (patch) | |
tree | e087e3428090111c5c41eeabe924a60d8078f338 /src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl | |
parent | f1a3503459317a19d0070d0569c31a41cccf4940 (diff) |
mb/lenovo/thinkcentre_a58: Add mainboard
The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output
TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation
TESTED with SeaBIOS (sercon disabled), Linux 4.19
Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl')
-rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..4540ce814d --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0004ffff, 0, 0, 0x14}, + Package() { 0x0004ffff, 1, 0, 0x15}, + Package() { 0x0004ffff, 2, 0, 0x16}, + Package() { 0x0004ffff, 3, 0, 0x17}, + + Package() { 0x0008ffff, 0, 0, 0x14}, + + Package() { 0x000affff, 0, 0, 0x15}, + Package() { 0x000affff, 1, 0, 0x16}, + Package() { 0x000affff, 2, 0, 0x17}, + Package() { 0x000affff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} |