diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-04-28 11:18:43 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-06 10:25:11 +0000 |
| commit | e4b2f3a6a2ecae9375f3014461b989e629d83410 (patch) | |
| tree | d8f904833376abe8f987746f8b5ee388a7d9fb7f /src/mainboard/lenovo/t520 | |
| parent | 2de0e8762225265fcf5b72b9d2b9b291f57af50c (diff) | |
mb/lenovo/*: Set VR12 PSI to fix crash
When in Package C3 or deeper the PSI settings are used to switch the
CPU VR into a low power state. It was found that the voltage regulator
on the Sandy-Bridge series has non-default PSI settings, compared to
Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3
as the vendor BIOS does to fix a hang when the package is idle.
Since neither the vendor BIOS is open-source, nor datasheet exists for
the used VR it's unclear why those PSI values must be used and how
they influence the regulator.
The X220 already has the correct PSI values configured and is now stable
for more than 24h in Package C7 state.
TEST: Not tested on the affected boards, only checked vendor firmware.
Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t520')
| -rw-r--r-- | src/mainboard/lenovo/t520/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c34d7..5edb63e95d 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit |