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authorKeith Hui <buurin@gmail.com>2023-07-22 12:49:05 -0400
committerFelix Held <felix-coreboot@felixheld.de>2023-11-13 20:31:23 +0000
commit45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch)
tree8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/lenovo/t520
parent940fe080bf1ed2dac827b569c70fb0ea11496041 (diff)
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t520')
-rw-r--r--src/mainboard/lenovo/t520/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/t520/early_init.c1
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/overridetree.cb1
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/romstage.c9
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/overridetree.cb1
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/romstage.c11
6 files changed, 2 insertions, 22 deletions
diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc
index a3b838ba10..69ef08873b 100644
--- a/src/mainboard/lenovo/t520/Makefile.inc
+++ b/src/mainboard/lenovo/t520/Makefile.inc
@@ -2,7 +2,6 @@
bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
-romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c
index 54d42ea3dc..219ffc1751 100644
--- a/src/mainboard/lenovo/t520/early_init.c
+++ b/src/mainboard/lenovo/t520/early_init.c
@@ -4,7 +4,6 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <device/device.h>
diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
index b976d6d904..d1634f81d6 100644
--- a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb
@@ -1,4 +1,5 @@
chip northbridge/intel/sandybridge
+ register "spd_addresses" = "{0x50, 0, 0x51, 0}"
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1f.0 on # LPC bridge
diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c
deleted file mode 100644
index cf5b18d4f2..0000000000
--- a/src/mainboard/lenovo/t520/variants/t520/romstage.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <northbridge/intel/sandybridge/raminit_native.h>
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[2], 0x51, id_only);
-}
diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
index 3e1c90ee63..4e03e753f4 100644
--- a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
+++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb
@@ -1,4 +1,5 @@
chip northbridge/intel/sandybridge
+ register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1c.6 on end # PCIe Port #7 USB 3.0
diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c
deleted file mode 100644
index 493a0a05ff..0000000000
--- a/src/mainboard/lenovo/t520/variants/w520/romstage.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <northbridge/intel/sandybridge/raminit_native.h>
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[1], 0x52, id_only);
- read_spd(&spd[2], 0x51, id_only);
- read_spd(&spd[3], 0x53, id_only);
-}