diff options
| author | Nicolas Reinecke <nr@das-labor.org> | 2014-08-23 01:06:33 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-23 18:43:39 +0200 |
| commit | 6ccc3465c3488411e6e743bb9a2822ac5902b6df (patch) | |
| tree | 89cf846b9435c8754eba466e305753b3298747b3 /src/mainboard/lenovo/t520/devicetree.cb | |
| parent | 23aad4a83c3390dc39f7d1c1f5422f7ac54a80f3 (diff) | |
lenovo/t520: fix devicetree
SATA Port documentation
PCIe unused ports and documentation
T520 have no keyboard backlight
Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/6743
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/lenovo/t520/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/t520/devicetree.cb | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 475e49c02c..c911d997fe 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -34,6 +34,7 @@ chip northbridge/intel/sandybridge device domain 0 on device pci 00.0 on end # host bridge + device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -54,7 +55,7 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi8_routing" = "2" - # Enable SATA ports 0 + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x1f" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" @@ -73,11 +74,14 @@ chip northbridge/intel/sandybridge device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end - device pci 1c.3 on end # PCIe Port #3 Express Card - device pci 1c.4 on end # PCIe Port #4 MMC/SDXC + IEEE1394 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 + device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY + device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 @@ -100,8 +104,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xc2" - register "has_keyboard_backlight" = "1" - register "beepmask0" = "0x00" register "beepmask1" = "0x86" register "has_power_management_beeps" = "0" |