nb/intel/haswell: Consolidate memory-down SPD handling

Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.

Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 7aca7c5351..7840a1fffa 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -40,10 +40,10 @@ void mb_late_romstage_setup(void)
 	}
 }
 
-void mb_get_spd_map(uint8_t spd_map[4])
+void mb_get_spd_map(struct spd_info *spdi)
 {
-	spd_map[0] = 0xa0;
-	spd_map[2] = 0xa2;
+	spdi->addresses[0] = 0xa0;
+	spdi->addresses[2] = 0xa2;
 }
 
 const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {