mainboard: Add Lenovo ThinkPad T440p

The code is based on autoport.

This port is tested on a T440p without a dGPU and can boot Arch Linux
from SATA disk with SeaBIOS payload. The tested components and issues
are in the documentation.

Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 113 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb
new file mode 100644
index 0000000000..7e5e616d03
--- /dev/null
+++ b/src/mainboard/lenovo/t440p/devicetree.cb
@@ -0,0 +1,113 @@
+chip northbridge/intel/haswell
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+	register "gfx.ndid" = "3"
+	register "gpu_cpu_backlight" = "0x12ba12ba"
+	register "gpu_ddi_e_connected" = "1"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_port_select" = "0"
+	register "gpu_panel_power_backlight_off_delay" = "1"
+	register "gpu_panel_power_backlight_on_delay" = "1"
+	register "gpu_panel_power_cycle_delay" = "6"
+	register "gpu_panel_power_down_delay" = "500"
+	register "gpu_panel_power_up_delay" = "2000"
+	register "gpu_pch_backlight" = "0x12ba12ba"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/haswell
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0x0 on
+		subsystemid 0x17aa 0x220e inherit
+
+		device pci 00.0 on end # Host bridge Host bridge
+		device pci 01.0 on end # PCIe Bridge for discrete graphics
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 03.0 on end # Mini-HD audio Audio controller
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen4_dec" = "0x000c06a1"
+			register "gpi13_routing" = "2"
+			register "gpi1_routing" = "2"
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8a"
+			register "pirqd_routing" = "0x89"
+			register "pirqe_routing" = "0x86"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x8b"
+			register "pirqh_routing" = "0x87"
+			register "sata_ahci" = "1"
+			# 0(HDD), 1(M.2), 5(ODD)
+			register "sata_port_map" = "0x23"
+			device pci 14.0 on end # xHCI Controller
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 on end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio Audio controller
+			device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader
+			device pci 1c.1 on # PCIe Port #2, WLAN
+				smbios_slot_desc "0x14" "1" "M.2 2230" "8"
+			end
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				chip ec/lenovo/pmh7
+					register "backlight_enable" = "0x01"
+					register "dock_event_enable" = "0x01"
+					device pnp ff.1 on # dummy
+					end
+				end
+				chip ec/lenovo/h8
+					register "beepmask0" = "0x00"
+					register "beepmask1" = "0x86"
+					register "config0" = "0xa6"
+					register "config1" = "0x0d"
+					register "config2" = "0xa8"
+					register "config3" = "0xc4"
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xd0"
+					register "event5_enable" = "0x3c"
+					register "event7_enable" = "0x01"
+					register "event8_enable" = "0x7b"
+					register "event9_enable" = "0xff"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+					register "evente_enable" = "0x9d"
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end