diff options
| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/lenovo/t430s/variants | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t430s/variants')
| -rw-r--r-- | src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t430s/variants/t430s/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t430s/variants/t431s/romstage.c | 19 |
3 files changed, 7 insertions, 21 deletions
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 4250665e2c..698460b1dc 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable hotplug on Port 5 for Thunderbolt controller diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c index c6414863ce..8980572174 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c @@ -3,7 +3,7 @@ #include <option.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <types.h> @@ -25,12 +25,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* P13: camera, no OC */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - void mainboard_early_init(int s3resume) { u8 enable_peg = get_uint_option("enable_dual_graphics", 0); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 54236a1ffc..6fbbaadbf4 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <cbfs.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <string.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <ec/lenovo/pmh7/pmh7.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, /* SSP1: right */ @@ -24,15 +20,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, -1 }, /* B1P6: Camera */ }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) +void mb_get_spd_map(struct spd_info *spdi) { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ - size_t spd_file_len = 0; - void *spd_file = cbfs_map("spd.bin", &spd_file_len); - - if (!spd_file || spd_file_len < sizeof(spd_raw_data)) - die("SPD data for C1S0 not found."); - - memcpy(&spd[0], spd_file, spd_file_len); - read_spd(&spd[2], 0x51, id_only); + spdi->addresses[0] = SPD_MEMORY_DOWN; + spdi->addresses[2] = 0x51; + spdi->spd_index = 0; } |