mainboard/lenovo/t430s: Add ThinkPad T431s as a variant

The code is based on autoport and that for T430s

Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
  Linux payload (Heads), Seabios may also work.

Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram

Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
  corresponding SPD datum (3 observed) from CBFS (the mechanism may be
  similar to that on x1_carbon_gen1 and s230u, but I do not know how
  to find gpio ports for that, and SPD data stored in vendor firmware.)

Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

14 files changed, 990 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/t430s/variants/t430s/board_info.txt b/src/mainboard/lenovo/t430s/variants/t430s/board_info.txt
new file mode 100644
index 0000000000..783d563064
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board name: ThinkPad T430s
+ROM package: SOIC-8 / WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/data.vbt b/src/mainboard/lenovo/t430s/variants/t430s/data.vbt
new file mode 100644
index 0000000000..75931547d3
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/data.vbt
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/gpio.c b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c
new file mode 100644
index 0000000000..56fb578b7e
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/gpio.c
@@ -0,0 +1,303 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,
+	.gpio1  = GPIO_MODE_GPIO,   // -EC_SCI - input
+	.gpio2  = GPIO_MODE_GPIO,
+	.gpio3  = GPIO_MODE_GPIO,
+	.gpio4  = GPIO_MODE_GPIO,
+	.gpio5  = GPIO_MODE_GPIO,
+	.gpio6  = GPIO_MODE_GPIO,
+	.gpio7  = GPIO_MODE_GPIO,
+	.gpio8  = GPIO_MODE_GPIO,
+	.gpio9  = GPIO_MODE_NATIVE, // OC5 - -USB_PORT9_OC5 - input
+	.gpio10 = GPIO_MODE_GPIO,   // DRAMRST_GATE_ON - output
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,   // -EC_WAKE - input
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0  = GPIO_DIR_INPUT,
+	.gpio1  = GPIO_DIR_INPUT,
+	.gpio2  = GPIO_DIR_INPUT,
+	.gpio3  = GPIO_DIR_INPUT,
+	.gpio4  = GPIO_DIR_INPUT,
+	.gpio5  = GPIO_DIR_INPUT,
+	.gpio6  = GPIO_DIR_INPUT,
+	.gpio7  = GPIO_DIR_INPUT,
+	.gpio8  = GPIO_DIR_OUTPUT,
+	.gpio9  = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0  = GPIO_LEVEL_LOW,
+	.gpio1  = GPIO_LEVEL_HIGH,
+	.gpio2  = GPIO_LEVEL_LOW,
+	.gpio3  = GPIO_LEVEL_HIGH,
+	.gpio4  = GPIO_LEVEL_HIGH,
+	.gpio5  = GPIO_LEVEL_HIGH,
+	.gpio6  = GPIO_LEVEL_HIGH,
+	.gpio7  = GPIO_LEVEL_HIGH,
+	.gpio8  = GPIO_LEVEL_HIGH,
+	.gpio9  = GPIO_LEVEL_HIGH,
+	.gpio10 = GPIO_LEVEL_HIGH,
+	.gpio11 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio13 = GPIO_LEVEL_HIGH,
+	.gpio14 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_HIGH,
+	.gpio16 = GPIO_LEVEL_HIGH,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio18 = GPIO_LEVEL_HIGH,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio20 = GPIO_LEVEL_HIGH,
+	.gpio21 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_LOW,
+	.gpio23 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_HIGH,
+	.gpio26 = GPIO_LEVEL_HIGH,
+	.gpio27 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+	.gpio30 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1  = GPIO_INVERT,
+	.gpio6  = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+	.gpio18 = GPIO_NO_BLINK,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE, // OC1 -USB_PORT1_OC1 - input
+	.gpio41 = GPIO_MODE_NATIVE, // OC2 - pullup
+	.gpio42 = GPIO_MODE_NATIVE, // OC3 -USB_PORT2_OC3 - input
+	.gpio43 = GPIO_MODE_GPIO,   // SMB_3B_EN - output
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE, // OC0 -USB_PORT0_OC0 - input
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_OUTPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio47 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+	.gpio62 = GPIO_DIR_OUTPUT,
+	.gpio63 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_HIGH,
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio40 = GPIO_LEVEL_HIGH,
+	.gpio41 = GPIO_LEVEL_HIGH,
+	.gpio42 = GPIO_LEVEL_HIGH,
+	.gpio43 = GPIO_LEVEL_HIGH,
+	.gpio44 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_HIGH,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio47 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio52 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio54 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_HIGH,
+	.gpio56 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio58 = GPIO_LEVEL_HIGH,
+	.gpio59 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+	.gpio62 = GPIO_LEVEL_LOW,
+	.gpio63 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_HIGH,
+	.gpio65 = GPIO_LEVEL_HIGH,
+	.gpio66 = GPIO_LEVEL_HIGH,
+	.gpio67 = GPIO_LEVEL_HIGH,
+	.gpio68 = GPIO_LEVEL_LOW,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_LOW,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_HIGH,
+	.gpio73 = GPIO_LEVEL_HIGH,
+	.gpio74 = GPIO_LEVEL_HIGH,
+	.gpio75 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+		.blink		= &pch_gpio_set1_blink,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+	},
+};
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c
new file mode 100644
index 0000000000..f73434d53e
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*	Vendor Name    : Realtek
+ *	Vendor ID      : 0x10ec0269
+ *	Subsystem ID   : 0x17aa21fb
+ *	Revision ID    : 0x100203
+ */
+
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	// Codec Vendor / Device ID: Realtek ALC269VC
+	0x17aa21fb,	// Subsystem ID
+	0x00000013,	// Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0  - Payload */
+
+/* NID 0x01 - NodeInfo */
+	AZALIA_SUBVENDOR(0x0, 0x17AA21FB),
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+	AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+	AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+	AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+	AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+	AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140),
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+	AZALIA_PIN_CFG(0x0, 0x17, 0x411111F0),
+	AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830),
+	AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0),
+
+	0x01970804,
+	0x01870803,
+	0x01470740,
+	0x00970600,
+
+	AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0),
+	AZALIA_PIN_CFG(0x0, 0x1B, 0x411111F0),
+	AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205),
+	AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0),
+
+	/* Misc entries */
+	0x00370600,
+	0x00270600,
+	0x00B707C0, /* Enable PortB as Output with HP amp */
+	0x00D70740, /* Enable PortD as Output */
+	0x0017A200, /* Disable ClkEn of PortSenseTst */
+	0x0017C621, /* Slave Port - Port A used as microphone input for
+		       combo Jack
+		       Master Port - Port B used for Jack Presence Detect
+		       Enable Combo Jack Detection */
+	0x0017A208, /* Enable ClkEn of PortSenseTst */
+	0x00170500, /* Set power state to D0 */
+
+	/* --- Next Codec --- */
+
+/*	Vendor Name    : Intel
+ *	Vendor ID      : 0x80862806
+ *	Subsystem ID   : 0x80860101
+ *	Revision ID    : 0x100000
+ */
+	/* coreboot specific header */
+	0x80862806,	// Codec Vendor / Device ID: Intel PantherPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of IDs
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+	AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+	AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)
+};
+
+const u32 pc_beep_verbs[] = {
+	/* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+	0x02177a00,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
new file mode 100644
index 0000000000..ff307027ec
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
@@ -0,0 +1,13 @@
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			device pci 1f.0 on
+				chip ec/lenovo/h8
+					register "has_bdc_detection" = "1"
+					register "bdc_gpio_num" = "54"
+					register "bdc_gpio_lvl" = "0"
+				end
+			end # LPC Controller
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
new file mode 100644
index 0000000000..1b1c4b2b79
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <option.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0,  0 }, /* P0:, OC 0 */
+	{ 1, 1,  1 }, /* P1: (EHCI debug), OC 1 */
+	{ 1, 1,  3 }, /* P2:  OC 3 */
+	{ 1, 0, -1 }, /* P3: no OC */
+	{ 1, 2, -1 }, /* P4: no OC */
+	{ 1, 1, -1 }, /* P5: no OC */
+	{ 1, 1, -1 }, /* P6: no OC */
+	{ 0, 1, -1 }, /* P7: empty, no OC */
+	{ 1, 1, -1 }, /* P8: smart card reader, no OC */
+	{ 1, 0,  5 }, /* P9:  (EHCI debug), OC 5 */
+	{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
+	{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
+	{ 0, 0, -1 }, /* P12: wlan, no OC */
+	{ 1, 1, -1 }, /* P13: camera, no OC */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x51, id_only);
+}
+
+void mainboard_early_init(int s3resume)
+{
+	u8 enable_peg;
+	if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS)
+		enable_peg = 0;
+
+	bool power_en = pmh7_dgpu_power_state();
+
+	if (enable_peg != power_en)
+		pmh7_dgpu_power_enable(!power_en);
+
+	if (!enable_peg) {
+		// Hide disabled dGPU device
+		u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+		reg32 &= ~DEVEN_PEG10;
+
+		pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
+	}
+}
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/board_info.txt b/src/mainboard/lenovo/t430s/variants/t431s/board_info.txt
new file mode 100644
index 0000000000..bf054008b3
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board name: ThinkPad T431s baseboard
+ROM package: SOIC-8 / WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2013
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/data.vbt b/src/mainboard/lenovo/t430s/variants/t431s/data.vbt
new file mode 100644
index 0000000000..e59ee8333e
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/data.vbt
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/gpio.c b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c
new file mode 100644
index 0000000000..5e0684cf6c
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_NATIVE,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_NATIVE,
+	.gpio7 = GPIO_MODE_NATIVE,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_NATIVE,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_OUTPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_OUTPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio3 = GPIO_LEVEL_HIGH,
+	.gpio5 = GPIO_LEVEL_LOW,
+	.gpio10 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_NATIVE,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_OUTPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio47 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio43 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_NATIVE,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c
new file mode 100644
index 0000000000..179fba0500
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0269, /* Codec Vendor / Device ID: Realtek */
+	0x17aa2208, /* Subsystem ID */
+
+	0x0000000b, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x0, 0x17aa2208),
+
+	/* NID 0x12.  */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
+
+	/* NID 0x14.  */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+	/* NID 0x15.  */
+	AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+
+	/* NID 0x17.  */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x40008000),
+
+	/* NID 0x18.  */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x03a11030),
+
+	/* NID 0x19.  */
+	AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+	/* NID 0x1a.  */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+	/* NID 0x1b.  */
+	AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+
+	/* NID 0x1d.  */
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x40f38205),
+
+	/* NID 0x1e.  */
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+	0x80862806, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+
+	0x00000004, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+	/* NID 0x05.  */
+	AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+	/* NID 0x06.  */
+	AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+	/* NID 0x07.  */
+	AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
new file mode 100644
index 0000000000..e69f727f07
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
@@ -0,0 +1,75 @@
+chip northbridge/intel/sandybridge
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+
+	# Enable Panel as eDP and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_up_delay" = "2000"		# 200ms
+	register "gpu_panel_power_down_delay" = "500"		# 50ms
+	register "gpu_panel_power_backlight_on_delay" = "1"	# 0.1ms
+	register "gpu_panel_power_backlight_off_delay" = "1"	# 0.1ms
+	register "gpu_cpu_backlight" = "0x03d2"
+
+	device domain 0 on
+		device pci 00.0 on
+			subsystemid 0x17aa 0x2208
+		end # host bridge
+		device pci 01.0 off end # PCIe Bridge for discrete graphics
+		device pci 02.0 on
+			subsystemid 0x17aa 0x2208
+		end # Integrated Graphics Controller
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+			# Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock)
+			register "sata_port_map" = "0x13"
+			# T431s has no Express Card slot.
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+			device pci 14.0 on
+				subsystemid 0x17aa 0x2208
+			end # USB 3.0 Controller
+			device pci 1a.0 on
+				subsystemid 0x17aa 0x2208
+			end # USB Enhanced Host Controller #2
+			device pci 1b.0 on
+				subsystemid 0x17aa 0x2208
+			end # High Definition Audio Controller
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x17aa 0x2208
+				chip drivers/ricoh/rce822 # Ricoh cardreader
+					register "disable_mask" = "0x87"
+					register "sdwppol" = "0"
+					device pci 00.0 on # Ricoh SD card reader
+						subsystemid 0x17aa 0x2208
+					end
+				end
+			end
+			device pci 1c.1 on
+				subsystemid 0x17aa 0x2208
+			end # PCIe Port #2 Integrated Wireless LAN
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1d.0 on
+				subsystemid 0x17aa 0x2208
+			end # USB Enhanced Host Controller #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on
+				subsystemid 0x17aa 0x2208
+				chip ec/lenovo/h8
+					register "config0" = "0xa6"
+					register "config1" = "0x09"
+					register "config3" = "0xc0"
+					register "evente_enable" = "0x1d"
+					# T431s only has BT on wlan card
+					register "has_bdc_detection" = "0"
+				end
+			end # LPC Controller
+			device pci 1f.2 on
+				subsystemid 0x17aa 0x2208
+			end # 6 port SATA AHCI Controller
+			device pci 1f.3 on
+				subsystemid 0x17aa 0x2208
+			end # SMBus Controller
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
new file mode 100644
index 0000000000..66e28ad21a
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <option.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include <cbfs.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },  /* SSP1: right */
+	{ 1, 0, 1 },  /* SSP2: left, EHCI Debug */
+	{ 1, 1, 3 },  /* SSP3: dock usb3 */
+	{ 1, 1, -1 }, /* B0P4: wwan usb */
+	{ 1, 1, 2 },  /* B0P5: dock usb2 */
+	{ 0, 0, -1 }, /* B0P6 */
+	{ 0, 0, -1 }, /* B0P7 */
+	{ 1, 2, -1 }, /* B0P8: unknown */
+	{ 1, 0, -1 }, /* B1P1: smart card reader */
+	{ 0, 2, 5 },  /* B1P2 */
+	{ 1, 1, -1 }, /* B1P3: fingerprint reader */
+	{ 0, 0, -1 }, /* B1P4 */
+	{ 1, 1, -1 }, /* B1P5: wlan usb */
+	{ 1, 1, -1 }, /* B1P6: Camera */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	/* C1S0 is a soldered RAM with no real SPD. Use stored SPD.  */
+	size_t spd_file_len = 0;
+	void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+		&spd_file_len);
+
+	if (!spd_file || spd_file_len < sizeof(spd_raw_data))
+		die("SPD data for C1S0 not found.");
+
+	memcpy(&spd[0], spd_file, spd_file_len);
+	read_spd(&spd[2], 0x51, id_only);
+}
+
+void mainboard_early_init(int s3resume)
+{
+}
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc
new file mode 100644
index 0000000000..4b9ef55007
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Alexander Couzens <lynxis@fe80.eu>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES  = samsung_4gb  # 0b0010 4GiB
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex b/src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex
new file mode 100644
index 0000000000..544d57605d
--- /dev/null
+++ b/src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 04 00 00 01 03 52 01 08 0a 00 80 00
+6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 b6 3b
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00