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authorPatrick Rudolph <siro@das-labor.org>2017-08-08 13:13:51 +0200
committerMartin Roth <martinroth@google.com>2017-08-10 16:09:01 +0000
commitb794a69ce9b2cbb9d6565cf0f3ac609402ad680a (patch)
treef200de26860f1d7f1465bb604f29e08b29f6cbc1 /src/mainboard/lenovo/t430
parentdb27e3384a596aad4e33abf535a72d42f7aab1e8 (diff)
nb/intel/sandybridge/raminit: Add Kconfig option for fuses
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
Diffstat (limited to 'src/mainboard/lenovo/t430')
-rw-r--r--src/mainboard/lenovo/t430/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index d112ad4e92..2fe895a111 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -34,9 +34,6 @@ chip northbridge/intel/sandybridge
end
end
- # Override fuse bits that hard-code the value to 666 Mhz
- register "max_mem_clock_mhz" = "933"
-
device domain 0x0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"