diff options
| author | Jonas Moehle <ad-min@mailbox.org> | 2019-12-25 03:40:51 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 07:54:53 +0000 |
| commit | 1f088c87572697a4c31257d8d8063f2c10234750 (patch) | |
| tree | 29541f1e8f1cebf9666d3658f98cba2fe75d15b8 /src/mainboard/lenovo/t430/vboot-rwab.fmd | |
| parent | 5e5e789f9b115f7fb1e7c453cdf20df088ac893d (diff) | |
mb/lenovo/*: Add support for VBOOT on 12MiB devices
Enable VBOOT support on all devices that have a 12 MiB flash, using
RW_MAIN_A + RW_MAIN_B partition, allowing the use of tianocore payload
in both RW_MAIN_A, RW_MAIN_B and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_AB by default
The VBNV is intentionally not covered by the CMOS checksum.
Tested on x230 and T440p.
Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Jonas Moehle <ad-min@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/mainboard/lenovo/t430/vboot-rwab.fmd')
| -rw-r--r-- | src/mainboard/lenovo/t430/vboot-rwab.fmd | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t430/vboot-rwab.fmd b/src/mainboard/lenovo/t430/vboot-rwab.fmd new file mode 100644 index 0000000000..1747c0e708 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-rwab.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A 0x280000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + RW_SECTION_B 0x280000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) + RW_FWID_B 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} |