diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2022-11-14 16:33:42 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2023-03-08 04:13:46 +0000 |
| commit | e930360bbe2239723ea9f7c493860053a069e71f (patch) | |
| tree | e8123a6c4aa8830dc466585ef9cdfe058f77a459 /src/mainboard/lenovo/t420s/vboot-rwa.fmd | |
| parent | 66c1d0dd3252b39220a4c50b7a4571cac82d6209 (diff) | |
mb/lenovo: Enable VBOOT_VBNV_FLASH
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for lenovo boards: t400, t410, t420, t420s, t430,
t430s, t520, t530, x131e, x1_carbon_gen1, x60, x200, x201, x220, x230. A
0x2000 RW_NVRAM region is allocated for them, with the COREBOOT size
reduced by 0x2000.
Also remove the VBOOT_VBNV_OFFSET config, since it's only used for
VBOOT_VBNV_CMOS.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
BUG=b:235293589
TEST=./util/abuild/abuild -t LENOVO_T430S -a # with VBOOT enabled
Change-Id: I7e29db7eeceec499fbbcf902a26bfe9a2076de40
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/lenovo/t420s/vboot-rwa.fmd')
| -rw-r--r-- | src/mainboard/lenovo/t420s/vboot-rwa.fmd | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd index 8a4cd3b477..4bd4b86528 100644 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -16,14 +16,15 @@ FLASH@0xff800000 0x800000 { } RW_VPD(PRESERVE)@0x1a0000 0x1000 SMMSTORE(PRESERVE)@0x1a1000 0x40000 + RW_NVRAM(PRESERVE)@0x1e1000 0x2000 - WP_RO@0x1e1000 0x11f000 { + WP_RO@0x1e3000 0x11d000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_PADDING@0x840 0x7c0 RO_VPD(PRESERVE)@0x1000 0x1000 GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 + COREBOOT(CBFS)@0x20000 0xfd000 } } } |