diff options
| author | Marcello Sylvester Bauer <sylv@sylv.io> | 2020-02-19 10:05:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:55:58 +0000 |
| commit | dd1a0acc4a1a08d3ff446fa84c41307eead91f11 (patch) | |
| tree | 24851f3c0a25d4b649f8aa0bdb12393c0f9d5c5a /src/mainboard/lenovo/t420 | |
| parent | 15161d92842e95f4b8ab10e4b1be118756fde437 (diff) | |
mb/lenovo: Add additional FMAPs on 8MiB devices
* Add FMAP for measured boot only, with a single RO partition.
* Add FMAP for measured boot only, with a single RO partition
but where the ME has been shrunken.
Tested on X220 using VBOOT+measured boot:
* Used patched IFD and ME, boots into OS
Change-Id: I04c1add13198444638c669deec1e05159b1a09c9
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t420')
| -rw-r--r-- | src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd | 22 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t420/vboot-ro.fmd | 22 |
2 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd new file mode 100644 index 0000000000..d1cbff7a1b --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x20000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS 0x7e0000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/t420/vboot-ro.fmd b/src/mainboard/lenovo/t420/vboot-ro.fmd new file mode 100644 index 0000000000..51df8a5322 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-ro.fmd @@ -0,0 +1,22 @@ +FLASH@0xff800000 0x800000 { + SI_ALL 0x500000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME 0x4ed000 + } + SI_BIOS 0x300000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } + } +} |