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authorKeith Hui <buurin@gmail.com>2024-02-05 16:11:26 -0500
committerMartin L Roth <gaumless@gmail.com>2024-06-07 22:39:18 +0000
commitc36b5ea18983e3dbb021ae3012698d1357dcdf66 (patch)
treef2575cdcf079c721cf89bba887cf2d28b791a256 /src/mainboard/lenovo/t420
parent51a01bdcd65370c29342f51a29fa5741447f09dc (diff)
mb/*: Copy bd82x6x boards' USB port config into devicetree
For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/t420')
-rw-r--r--src/mainboard/lenovo/t420/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index d469da6b79..6b721f3f74 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -58,6 +58,24 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
+ # OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
+ register "usb_port_config" = "{
+ {1, 1, 0}, /* P0: system port 4, OC0 */
+ {1, 1, 1}, /* P1: system port 2 (EHCI debug), OC 1 */
+ {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */
+ {1, 0, -1}, /* P3: WWAN, no OC */
+ {1, 0, -1}, /* P4: smartcard, no OC */
+ {1, 1, -1}, /* P5: ExpressCard, no OC */
+ {0, 0, -1}, /* P6: empty */
+ {0, 0, -1}, /* P7: empty */
+ {1, 1, 4}, /* P8: system port 3, OC4*/
+ {1, 1, 5}, /* P9: system port 1 (EHCI debug), OC 5 */
+ {1, 0, -1}, /* P10: fingerprint reader, no OC */
+ {1, 0, -1}, /* P11: bluetooth, no OC. */
+ {1, 1, -1}, /* P12: docking, no OC */
+ {1, 1, -1} /* P13: camera (LCD), no OC */
+ }"
+
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R