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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-16 16:22:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 20:11:24 +0000
commit6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd (patch)
tree54f4bdf90f1e9ecc9b377b084bfb44396ee0693a /src/mainboard/lenovo/t420
parentc7a3152273ef3179e3ad5f66f53c4a9d2aa39c8e (diff)
treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t420')
-rw-r--r--src/mainboard/lenovo/t420/early_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index 2e39885b6b..c675512d6f 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -48,7 +48,7 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
-// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
+// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0: system port 4, OC0 */
{ 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */