diff options
author | Nicolas Reinecke <nr@das-labor.org> | 2015-10-01 15:34:37 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-04-13 17:54:46 +0200 |
commit | 2bffa8aa8418a7029615b492c80508733bba1231 (patch) | |
tree | cf3dc5e64b04d684e343617431267355fbe72d5e /src/mainboard/lenovo/t420/dsdt.asl | |
parent | 888a98b872ed88f70b76103a95ef5d4140cfe2d7 (diff) |
lenovo/t420: Add new port
This is based on t420s. Tested on a T420 without discrete GPU.
There is no support for nvidia gpu and optimus.
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
Reviewed-on: https://review.coreboot.org/11765
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/lenovo/t420/dsdt.asl')
-rw-r--r-- | src/mainboard/lenovo/t420/dsdt.asl | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl new file mode 100644 index 0000000000..aaa033840f --- /dev/null +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} |