mainboard/lenovo/t410: Add new port

The port is based on the x201 / t410s.
2537-vg5 / i5, no discrete gpu

Tested and working:
* Native raminit
* Native gfxinit
* Booting Seabios 1.12.1
* Booting from EHCI
* Running GNU/Linux 5.0.0
* No errors in dmesg
* EHCI debug on the devices left side, bottom-right
* Keyboard
* Fn keys (Mute, Volume, Mic)
* Touchpad
* TPM
* Wifi
* Sound
* USB
* Ethernet
* S3 resume
* VBOOT

Testing in progress.

Untested:
* VGA
* Displayport
* Docking station

Bugs:
* AC adapter can't be read from ACPI
* TPM not working with VBOOT and C_ENV BB

Details for flashing externally:
1. Disconnect all power
2. Connect the external flasher
3. Connect the power cord (This fixes internal power control)
4. Remove the power cord

Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 95 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl
new file mode 100644
index 0000000000..08e21225ca
--- /dev/null
+++ b/src/mainboard/lenovo/t410/dsdt.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20130325	/* OEM revision */
+)
+{
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+	/* Some generic macros */
+	#include "acpi/platform.asl"
+
+	/* global NVS and variables */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	/* General Purpose Events */
+	#include "acpi/gpe.asl"
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/nehalem/acpi/nehalem.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		}
+		Device (UNCR)
+		{
+			Name (_BBN, 0xFF)
+			Name (_ADR, 0x00)
+			Name (RID, 0x00)
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_CRS, ResourceTemplate ()
+				{
+				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+						0x0000,	     /* Granularity */
+						0x00FF,	     /* Range Minimum */
+						0x00FF,	     /* Range Maximum */
+						0x0000,	     /* Translation Offset */
+						0x0001,	     /* Length */
+						,, )
+				})
+			Device (SAD)
+			{
+				Name (_ADR, 0x01)
+				Name (RID, 0x00)
+				OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+				Field (SADC, DWordAcc, NoLock, Preserve)
+				{
+					Offset (0x40),
+					PAM0,   8,
+					PAM1,   8,
+					PAM2,   8,
+					PAM3,   8,
+					PAM4,   8,
+					PAM5,   8,
+					PAM6,   8
+				}
+			}
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+	/* Dock support code */
+	#include "acpi/dock.asl"
+}