diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2018-04-23 20:02:35 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-10-29 11:26:02 +0000 |
| commit | 8950706169a32764f3c4dc536cae397b463c390f (patch) | |
| tree | 498304913db88ef75610f827375263ccd170df03 /src/mainboard/lenovo/t400 | |
| parent | 82b1e019a5072617a87ffa728088e9c9c338ca68 (diff) | |
mb/lenovo/t400: Use acpi_s3_resume_allowed()
Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed())
also to the Lenovo T400.
See also commit 42ae0bae with Change-Id
I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 (mb/lenovo/x200: Use
acpi_s3_resume_allowed())
Change-Id: I9d4ac711375977a979a8b3e5606e2197847e88de
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/t400')
| -rw-r--r-- | src/mainboard/lenovo/t400/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 7bf14bff19..bc419bf7d0 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -101,16 +101,16 @@ void mainboard_romstage_entry(unsigned long bist) /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } } /* RAM initialization */ |