aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/s230u/devicetree.cb
diff options
context:
space:
mode:
authorTobias Diedrich <ranma+openocd@tdiedrich.de>2017-02-12 14:09:06 +0100
committerMartin Roth <martinroth@google.com>2017-02-20 18:21:56 +0100
commitcee930a39b183260ea83ac72fc9ca59d61353d8d (patch)
treeb3fd18b7a202b837fc512e2b71a599956fdbbdee /src/mainboard/lenovo/s230u/devicetree.cb
parent97535558f1a1c123a60d73244d835ff5d8d31213 (diff)
lenovo/s230u: Add Thinkpad Twist (S230U)
Created using autoport plus some manual work and copying from G505S to account for the non-H8 EC. This model uses the same ENE KB9012 EC as the G505S. Tested: - Mainboard variant with 8GB Elpida DDR3 - SeaBIOS payload - Booting into Linux 4.9.6 with Debian/unstable installed on the internal HDD/SDD slot - Native raminit - Both native VGA init and option rom VGA init - Basic TPM functionality (auto-detection and RNG) - Battery status readout - Basic ACPI functions (power button event; power-off; reboot) - thinkpad-acpi hotkey functions - thinkpad-acpi LED control (red thinkpad LED) - Suspend to RAM and resume works - Mini displayport output works Known issues: - Patches needed for EC battery support https://review.coreboot.org/#/c/18348/ https://review.coreboot.org/#/c/18349/ - No thermal zone since temperature sensing is not H8-compatible and needs to be reverse engineered. Not tested: - msata/wwan (probably works) Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c Reviewed-on: https://review.coreboot.org/18351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/s230u/devicetree.cb')
-rw-r--r--src/mainboard/lenovo/s230u/devicetree.cb138
1 files changed, 138 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb
new file mode 100644
index 0000000000..ff4c6c4cff
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/devicetree.cb
@@ -0,0 +1,138 @@
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000060"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "600"
+ register "gpu_pch_backlight" = "0x041e041e"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x17aa 0x2205
+ end
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x00000000"
+ register "gen2_dec" = "0x000c0701"
+ register "gen3_dec" = "0x000c0069"
+ register "gen4_dec" = "0x000c06a1"
+ register "gpi13_routing" = "2"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x11"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 16.0 off # Management Engine Interface 1
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 on # PCIe Port #4
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x17aa 0x2205
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x17aa 0x2205
+ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
+ device i2c 54 on
+ end
+ device i2c 55 on
+ end
+ device i2c 56 on
+ end
+ device i2c 57 on
+ end
+ device i2c 5c on
+ end
+ device i2c 5d on
+ end
+ device i2c 5e on
+ end
+ device i2c 5f on
+ end
+ end
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ end
+end