diff options
| author | Maciej Pijanowski <maciej.pijanowski@3mdeb.com> | 2024-01-17 23:47:44 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-11-05 20:34:19 +0000 |
| commit | d28fedf4f2cb7e4475a6cdfcab37d64cc60bba1f (patch) | |
| tree | 23b3d4863b1028b48efcb0191e43b00973cfe06b /src/mainboard/lenovo/m920q/bootblock.c | |
| parent | f48dd169954716562bc88f9ecb25d38d63c18f8d (diff) | |
mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here.
Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
- PCIe x8 port (x8 riser tested, x4 not)
Does not work:
- front audio jacks
Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/m920q/bootblock.c')
| -rw-r--r-- | src/mainboard/lenovo/m920q/bootblock.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/m920q/bootblock.c b/src/mainboard/lenovo/m920q/bootblock.c new file mode 100644 index 0000000000..7839cf7fb8 --- /dev/null +++ b/src/mainboard/lenovo/m920q/bootblock.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6687D_SP2) +#define POWER_DEV PNP_DEV(0x2e, NCT6687D_SLEEP_PWR) + +void bootblock_mainboard_early_init(void) +{ + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x13, 0xff); + pnp_write_config(SERIAL_DEV, 0x14, 0xff); + + /* Below are multi-pin function */ + pnp_write_config(SERIAL_DEV, 0x1b, 0xf8); + pnp_write_config(SERIAL_DEV, 0x1f, 0xf0); + pnp_write_config(SERIAL_DEV, 0x20, 0xd4); + pnp_write_config(SERIAL_DEV, 0x21, 0x41); + pnp_write_config(SERIAL_DEV, 0x22, 0xbc); + pnp_write_config(SERIAL_DEV, 0x23, 0xff); + pnp_write_config(SERIAL_DEV, 0x24, 0x07); + pnp_write_config(SERIAL_DEV, 0x25, 0xff); + pnp_write_config(SERIAL_DEV, 0x26, 0x80); + pnp_write_config(SERIAL_DEV, 0x28, 0x08); + pnp_write_config(SERIAL_DEV, 0x29, 0x95); + pnp_write_config(SERIAL_DEV, 0x2a, 0xcf); + + pnp_set_logical_device(POWER_DEV); + /* Configure pin for PECI */ + pnp_write_config(POWER_DEV, 0xf3, 0x18); + + nuvoton_pnp_exit_conf_state(POWER_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} |