summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/l520
diff options
context:
space:
mode:
authorPeter Lemenkov <lemenkov@gmail.com>2019-11-27 22:39:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-09 09:48:51 +0000
commit7e128576c2abe440a1b39a723f55b9e139c3cf1c (patch)
tree0260fb535a599f4aa9c1917a18cd8aa9d9705a69 /src/mainboard/lenovo/l520
parent5ee7e472d1fb836b04f6fde3368ab8fb8aa9a08a (diff)
mb/lenovo/l520/devicetree: Use subsystemid inheritance
Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/lenovo/l520')
-rw-r--r--src/mainboard/lenovo/l520/devicetree.cb122
1 files changed, 39 insertions, 83 deletions
diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 024b8f8dd1..29b75984fb 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_up_delay" = "0"
register "gpu_pch_backlight" = "0x00000000"
- device cpu_cluster 0x0 on
+ device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
@@ -28,15 +28,13 @@ chip northbridge/intel/sandybridge
end
end
- device domain 0x0 on
- device pci 00.0 on # Host bridge Host bridge
- subsystemid 0x17aa 0x21dd
- end
- device pci 01.0 on # PCIe Bridge for discrete graphics
- end
- device pci 02.0 on # Internal graphics VGA controller
- subsystemid 0x17aa 0x21dd
- end
+ device domain 0 on
+ subsystemid 0x17aa 0x21dd inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1"
@@ -54,57 +52,28 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0"
register "spi_lvscc" = "0x2005"
- device pci 16.0 on # Management Engine Interface 1
- subsystemid 0x17aa 0x21dd
- end
- device pci 16.1 off # Management Engine Interface 2
- end
- device pci 16.2 off # Management Engine IDE-R
- end
- device pci 16.3 off # Management Engine KT
- end
- device pci 19.0 off # Intel Gigabit Ethernet
- end
- device pci 1a.0 on # USB2 EHCI #2
- subsystemid 0x17aa 0x21dd
- end
- device pci 1b.0 on # High Definition Audio Audio controller
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.0 on # PCIe Port #1
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.1 on # PCIe Port #2
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.2 on # PCIe Port #3
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.3 on # PCIe Port #4
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.4 on # PCIe Port #5
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.5 on # PCIe Port #6
- subsystemid 0x17aa 0x21dd
- end
- device pci 1c.6 off # PCIe Port #7
- end
- device pci 1c.7 off # PCIe Port #8
- end
- device pci 1d.0 on # USB2 EHCI #1
- subsystemid 0x17aa 0x21dd
- end
- device pci 1e.0 off # PCI bridge
- end
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge
- subsystemid 0x17aa 0x21dd
chip ec/lenovo/pmh7
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
- device pnp ff.1 on # dummy
- end
+ device pnp ff.1 on end # dummy
end
chip ec/lenovo/h8
register "config0" = "0xa7"
@@ -136,35 +105,22 @@ chip northbridge/intel/sandybridge
io 0x66 = 0x1604
end
end
- end
- device pci 1f.2 on # SATA Controller 1
- subsystemid 0x17aa 0x21dd
- end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on # SMBus
- subsystemid 0x17aa 0x21dd
chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
- device i2c 54 on
- end
- device i2c 55 on
- end
- device i2c 56 on
- end
- device i2c 57 on
- end
- device i2c 5c on
- end
- device i2c 5d on
- end
- device i2c 5e on
- end
- device i2c 5f on
- end
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
end
- end
- device pci 1f.5 off # SATA Controller 2
- end
- device pci 1f.6 off # Thermal
- end
+ end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
end
end
end