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authorPatrick Rudolph <siro@das-labor.org>2016-12-30 17:02:04 +0100
committerMartin Roth <martinroth@google.com>2017-01-24 18:20:40 +0100
commitaae6e9cfe9cc2fd301cd07d2ddc0f5f826118550 (patch)
tree4f97bed2eb7b2a2b78d3893df934a0c1f7c0d681 /src/mainboard/lenovo/l520/cmos.layout
parent847bbb8b1b8dd38b578a2bec3abdfcc4c6925c7a (diff)
mainboard/lenovo: Add new port L520
Add support for Lenovo Thinkpad L520. The files are generated by autoport, and are successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extract the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Management Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load SeaBIOS. Latest debian has been booted from harddisk. Latest fedora has been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound) Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18003 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/l520/cmos.layout')
-rw-r--r--src/mainboard/lenovo/l520/cmos.layout143
1 files changed, 143 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout
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+++ b/src/mainboard/lenovo/l520/cmos.layout
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+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+#419 2 r 0 unused
+421 1 e 9 sata_mode
+422 2 e 10 backlight
+
+# coreboot config options: cpu
+424 1 e 2 hyper_threading
+#425 7 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+#437 3 r 0 unused
+440 8 h 0 volume
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 Both
+10 1 Keyboard only
+10 2 Thinklight only
+10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+12 0 Integrated Only
+12 1 Discrete Only
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984