mb/*/*: Remove AMD FAMILY15TN boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

26 files changed, 0 insertions, 1461 deletions

diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c
deleted file mode 100644
index dd4c42b968..0000000000
--- a/src/mainboard/lenovo/g505s/BiosCallOuts.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/agesa/state_machine.h>
-
-#include <southbridge/amd/agesa/hudson/imc.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * AMD Parmer Platform ALC272 Verb Table
- */
-static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = {
-	{0x11, 0x411111F0},
-	{0x12, 0x411111F0},
-	{0x13, 0x411111F0},
-	{0x14, 0x411111F0},
-	{0x15, 0x411111F0},
-	{0x16, 0x411111F0},
-	{0x17, 0x411111F0},
-	{0x18, 0x01a19840},
-	{0x19, 0x411111F0},
-	{0x1a, 0x01813030},
-	{0x1b, 0x411111F0},
-	{0x1d, 0x40130605},
-	{0x1e, 0x01441120},
-	{0x21, 0x01211010},
-	{0xff, 0xffffffff}
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
-	{0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]},
-	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
-
-/* Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM failed to read the input temperature via I2C,
- *  if other software switches the I2C switch by mistake or intention.
- *  We recommend using IMC to control Fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	/* Enable IMC fan control, the recommended way */
-	if (CONFIG(HUDSON_IMC_FWM)) {
-		imc_reg_init();
-
-		/* HwMonitorEnable = TRUE &&  HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
-
-		FchParams->Imc.ImcEnable = TRUE;
-		FchParams->Hwm.HwmControl = 1;	/* 1 IMC, 0 HWM */
-		FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-		LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
-		/* Thermal Zone Parameter */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00;	/* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;	/* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;	/* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
-
-		/* IMC Fan Policy temperature thresholds */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00;	/* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80;	/*AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c;	/*AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32;	/*AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff;	/*AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff;	/*AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff;	/*AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff;	/*AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff;	/*AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b;	/*critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-		/* IMC Fan Policy PWM Settings */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00;	/* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a;	/* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46;	/* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28;	/* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff;	/* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff;	/* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff;	/* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff;	/* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff;	/* AL7 percentage */
-
-		FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
-
-		/* NOTE:
-		 * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
-		 * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
-		 * So we remove it from AGESA code. Please See FchInitLateHwm.
-		 */
-	} else {
-		/* HWM fan control, the way not recommended */
-		FchParams->Imc.ImcEnable = FALSE;
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
-	}
-}
-
-void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
-{
-	FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-}
-
-void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
-{
-	/* Azalia Controller OEM Codec Table Pointer */
-	FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
-
-	/* Fan Control */
-	oem_fan_control(FchParams_env);
-}
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
deleted file mode 100644
index dbf8b68253..0000000000
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_LENOVO_G505S
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select SYSTEM_TYPE_LAPTOP
-	select CPU_AMD_AGESA_FAMILY15_TN
-	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
-	select SOUTHBRIDGE_AMD_AGESA_HUDSON
-	select DEFAULT_POST_ON_LPC
-	select EC_COMPAL_ENE932
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_SMI_HANDLER
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-	select NO_UART_ON_SUPERIO
-
-config MAINBOARD_DIR
-	default "lenovo/g505s"
-
-config MAINBOARD_PART_NUMBER
-	default "LENOVO G505S"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,990b"
-
-config PAYLOAD_CONFIGFILE
-	string
-	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS
-
-endif # BOARD_LENOVO_G505S
diff --git a/src/mainboard/lenovo/g505s/Kconfig.name b/src/mainboard/lenovo/g505s/Kconfig.name
deleted file mode 100644
index ff3ca28e9b..0000000000
--- a/src/mainboard/lenovo/g505s/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_LENOVO_G505S
-	bool "AMD G505s"
diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc
deleted file mode 100644
index 5d42edabf4..0000000000
--- a/src/mainboard/lenovo/g505s/Makefile.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-ramstage-y += ec.c
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
deleted file mode 100644
index 80daf19afe..0000000000
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <Porting.h>
-#include <AGESA.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-/*
- * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
- *
- * Lane Id
- * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
- * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
- * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
- * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
- * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
- * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
- * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
- * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
- * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
- * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
- * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
- * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
- * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
- * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
- * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
- * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
- * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
- * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
- * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
- * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
- * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
- * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
- * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
- * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
- * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
- * 25 DP0_TX[P,N]1
- * 26 DP0_TX[P,N]2
- * 27 DP0_TX[P,N]3
- * 28 DP1_TX[P,N]0
- * 29 DP1_TX[P,N]1
- * 30 DP1_TX[P,N]2
- * 31 DP1_TX[P,N]3
- * 32 DP2_TX[P,N]0
- * 33 DP2_TX[P,N]1
- * 34 DP2_TX[P,N]2
- * 35 DP2_TX[P,N]3
- * 36 DP2_TX[P,N]4
- * 37 DP2_TX[P,N]5
- * 38 DP2_TX[P,N]6
- */
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-	/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 1)
-	},
-
-	/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0)
-	},
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 to HDMI0/DP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-	/* DP1 to FCH */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
-	},
-	/* DP2 to HDMI1/DP */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
-{
-	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
-	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-	FchReset->Xhci1Enable = FALSE;
-}
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform
- * information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...).
- * If PlatformSpecificTable is populated, AGESA will base its settings on the
- * data from the table. Otherwise, it will use its default conservative settings
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-	CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
-	ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
-	CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
-
-void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
-{
-	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
-	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
-}
diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl
deleted file mode 100644
index cde03fac2c..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/ec.asl
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/* Defines EC bits specific to the mainboard, needed by EC ASL */
-#include "../mainboard.h"
-
-/* ACPI code for EC functions */
-#include <ec/compal/ene932/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl
deleted file mode 100644
index 74b4c4807b..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/gpe.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/* Legacy PM event */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/* Temp warning (TWarn) event */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/* USB controller PME# */
-	Method(_L0B) {
-		Printf ("USB PME")
-		/* Notify devices of wake event */
-		Notify(\_SB.PCI0.UOH1, 0x02)
-		Notify(\_SB.PCI0.UOH2, 0x02)
-		Notify(\_SB.PCI0.UOH3, 0x02)
-		Notify(\_SB.PCI0.UOH4, 0x02)
-		Notify(\_SB.PCI0.XHC0, 0x02)
-		Notify(\_SB.PCI0.UEH1, 0x02)
-	}
-
-	/* ExtEvent0 SCI event */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/* ExtEvent1 SCI event */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/* Lid switch opened or closed */
-	Method(_L16) {
-		Printf ("Lid status changed")
-		/* Flip trigger polarity */
-		LPOL = ~LPOL
-		/* Notify lid object of status change */
-		Notify(\_SB.LID, 0x80)
-	}
-
-	/* GPIO0 or GEvent8 event */
-	Method(_L18) {
-		Printf ("PCI bridge wake event")
-		/* Notify PCI bridges of wake event */
-		Notify(\_SB.PCI0.PBR4, 0x02)
-		Notify(\_SB.PCI0.PBR5, 0x02)
-	}
-
-	/* Azalia SCI event */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl
deleted file mode 100644
index 36f82a3335..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	/* AcpiGpe0Blk */
-	OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
-		Field(GP0B, ByteAcc, NoLock, Preserve) {
-		, 11,
-		USBS, 1,
-	}
-
-	/* GPIO control block -- hardcoded to 0xfed80100 by AGESA */
-	OperationRegion (GPIO, SystemMemory, 0xfed80100, 0x100)
-	Field (GPIO, ByteAcc, NoLock, Preserve) {
-		Offset (0x39),
-		, 6,
-		GP57, 1,	/* out: WLAN control (rf-kill) */
-		Offset (0x76),
-		, 7,
-		GE22, 1,	/* General event 22 - connected to lid switch */
-	}
-
-	/* SMI/SCI control block -- hardcoded to 0xfed80200 by AGESA */
-	OperationRegion (SMIX, SystemMemory, 0xfed80200, 0x100)
-	Field (SMIX, AnyAcc, NoLock, Preserve) {
-		Offset (0x08),	/* SCI level: 0 = active low, 1 = active high */
-		, 22,
-		LPOL, 1,	/* SCI22 trigger polarity - lid switch */
-	}
-
-	/*
-	 * Used by EC code on certain events
-	 *
-	 * From ec/compal/ene932/acpi/ec.asl:
-	 * The mainboard must define a PNOT method to handle power state
-	 * notifications and Notify CPU device objects to re-evaluate their
-	 * _PPC and _CST tables.
-	 */
-	Method (PNOT)
-	{
-		Printf ("Received PNOT call (probably from EC)")
-		/* TODO: Implement this */
-	}
-
-Scope (\_SB) {
-	Device (LID)
-	{
-		Name(_HID, EisaId("PNP0C0D"))
-		Name(_PRW, Package () {EC_LID_GPE, 0x04}) /* wake from S1-S4 */
-		Method(_LID, 0)
-		{
-			Return (GE22)	/* GE pin 22 */
-		}
-
-		Method (_INI, 0)
-		{
-			/* Make sure lid trigger polarity is set so that we
-			 * trigger an SCI when lid status changes.
-			 */
-			LPOL = ~GE22
-		}
-	}
-
-	Device (MB) {
-		Name(_HID, EisaId("PNP0C01")) // System Board
-
-		/* Lid open */
-		Method (LIDO) { /* Stub */ }
-		/* Lid closed */
-		Method (LIDC) { /* Stub */ }
-		/* Increase brightness */
-		Method (BRTU) { /* Stub */ }
-		/* Decrease brightness */
-		Method (BRTD) { /* Stub */ }
-		/* Switch display */
-		Method (DSPS) { /* Stub */ }
-		/* Toggle wireless */
-		Method (WLTG)
-		{
-			GP57 = ~GP57
-		}
-		/* Return lid state */
-		Method (LIDS)
-		{
-			Return(GE22)
-		}
-	}
-}
diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl
deleted file mode 100644
index 6f91672106..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/routing.asl
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	/* Routing is in System Bus scope */
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, INTB, 0 },
-		Package(){0x0001FFFF, 1, INTC, 0 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, INTC, 0 },
-		Package(){0x0010FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, 0, 17 },
-		Package(){0x0001FFFF, 1, 0, 18 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, 0, 0x12},
-		Package(){0x0010FFFF, 1, 0, 0x11},
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-	Name(PS6, Package(){
-	})
-	Name(APS6, Package(){
-	})
-	Name(PS7, Package(){
-	})
-	Name(APS7, Package(){
-	})
-	Name(PCIB, Package(){
-	})
diff --git a/src/mainboard/lenovo/g505s/acpi/sata.asl b/src/mainboard/lenovo/g505s/acpi/sata.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/sata.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl
deleted file mode 100644
index cd714cec87..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/sleep.asl
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-
-	UPWS = 0x07
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	USBS = 1
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl
deleted file mode 100644
index 6a6b217e17..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/superio.asl
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/* Defines EC bits specific to the mainboard, needed by EC ASL */
-#include "mainboard.h"
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/compal/ene932/acpi/superio.asl>
diff --git a/src/mainboard/lenovo/g505s/acpi/thermal.asl b/src/mainboard/lenovo/g505s/acpi/thermal.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/thermal.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl
deleted file mode 100644
index d90fffdd40..0000000000
--- a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins. */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/lenovo/g505s/board_info.txt b/src/mainboard/lenovo/g505s/board_info.txt
deleted file mode 100644
index c259823965..0000000000
--- a/src/mainboard/lenovo/g505s/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: laptop
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
-Release year: 2013
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
deleted file mode 100644
index 3bf316e4fd..0000000000
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "mainboard.h"
-
-#include <vendorcode/amd/agesa/f15tn/AGESA.h>
-
-/* Include the files that instantiate the configuration definitions. */
-#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
-/* AGESA nonsense: the next two headers depend on heapManager.h */
-#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
-/* These tables are optional and may be used to adjust memory timing settings */
-#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FS1_SOCKET_SUPPORT		TRUE
-#define INSTALL_FP2_SOCKET_SUPPORT		TRUE
-
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT		TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
-#define BLDOPT_REMOVE_SRAT			FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-#define BLDOPT_REMOVE_CRAT			TRUE
-
-/* Build configuration values here */
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-
-#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
-#define BLDCFG_ENABLE_ECC_FEATURE		TRUE
-#define BLDCFG_ECC_SYNC_FLOOD			FALSE
-
-#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
-#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
-
-#define BLDCFG_IOMMU_SUPPORT			TRUE
-
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-
-/*
- * The GPIO control is not well documented in AGESA, but is in the BKDG
- *
- * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
- * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
- * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
- * are mostly in Function1, sometimes Function2.
- *
- * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
- * actually controls the output value, so GpioOut means "default to set".
- * PullUpB is an inverted logic, so setting this bit means we're actually
- * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
- * The output driver can be disabled with the GpioOutEnB bit, which is again,
- * inverted logic. To make the list more readable, we define a few local macros
- * to state what we mean.
- */
-#define OUTPUT_HIGH	(GpioOut)
-#define OUTPUT_LOW	(0)
-#define INPUT		(GpioOutEnB)
-#define PULL_UP		(0)
-#define PULL_DOWN	(PullDown | PullUpB)
-#define PULL_NONE	(PullUpB)
-
-CONST GPIO_CONTROL lenovo_g505s_gpio[] = {
-	{57, Function1, OUTPUT_HIGH | PULL_NONE},	/* WLAN enable */
-	{-1}
-};
-#define BLDCFG_FCH_GPIO_CONTROL_LIST		(lenovo_g505s_gpio)
-
-/*
- * These definitions could be moved to a common Hudson header, should we decide
- * to provide our own, saner SCI mapping function
- */
-#define GEVENT_PIN(gpe)		((gpe) + 0x40)
-#define SCI_MAP_OHCI_12_0	0x58
-#define SCI_MAP_OHCI_13_0	0x59
-#define SCI_MAP_XHCI_10_0	0x78
-#define SCI_MAP_PWRBTN		0x73
-
-CONST SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
-	{GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
-	{GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
-	{GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
-	{SCI_MAP_OHCI_12_0, PME_GPE},
-	{SCI_MAP_OHCI_13_0, PME_GPE},
-	{SCI_MAP_XHCI_10_0, PME_GPE},
-	{SCI_MAP_PWRBTN, PME_GPE},
-};
-#define BLDCFG_FCH_SCI_MAP_LIST			(lenovo_g505s_sci_map)
-
-/*
- * Process the options...
- * This file include MUST occur AFTER the user option selection settings.
- * AGESA nonsense: Moving this include up will break AGESA.
- */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout
deleted file mode 100644
index 7354972180..0000000000
--- a/src/mainboard/lenovo/g505s/cmos.layout
+++ /dev/null
@@ -1,36 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-#400	8	r	8	reserved for century byte
-408	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/lenovo/g505s/config_seabios b/src/mainboard/lenovo/g505s/config_seabios
deleted file mode 100644
index 1959fa35c2..0000000000
--- a/src/mainboard/lenovo/g505s/config_seabios
+++ /dev/null
@@ -1,7 +0,0 @@
-###
-### SeaBIOS custom configuration for Lenovo G505S
-###
-# CONFIG_MEGASAS is not set
-# CONFIG_NVME is not set
-# CONFIG_TCGBIOS is not set
-#
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
deleted file mode 100644
index 4b4df367b1..0000000000
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ /dev/null
@@ -1,69 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family15tn/root_complex
-
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family15tn
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/family15tn
-			device pci 0.0 on  end # Root Complex
-			device pci 0.2 on  end # IOMMU
-			device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
-			device pci 1.1 on  end # Internal Multimedia
-			device pci 2.0 off end
-			device pci 3.0 off end
-			device pci 4.0 on  end # PCIE MINI0
-			device pci 5.0 on  end # PCIE MINI1
-			device pci 6.0 off end #
-			device pci 7.0 off end #
-			device pci 8.0 off end # NB/SB Link P2P bridge ?
-			device pci 9.0 off end #
-		end	#chip northbridge/amd/agesa/family15tn
-
-		chip southbridge/amd/agesa/hudson
-			device pci 10.0 on  end # FCH USB XHCI Controller HC0
-			device pci 11.0 on  end # FCH SATA Controller [AHCI mode]
-			device pci 12.0 on  end # FCH USB OHCI Controller
-			device pci 12.2 on  end # FCH USB EHCI Controller
-			device pci 13.0 on  end # FCH USB OHCI Controller
-			device pci 13.2 on  end # FCH USB EHCI Controller
-			device pci 14.0 on  end # SMBUS
-			device pci 14.2 on  end # FCH Azalia Controller
-			device pci 14.3 on      # FCH LPC Bridge [1022:780e]
-				chip ec/compal/ene932
-					# 60/64 KBC
-					device pnp ff.1 on end # dummy address
-				end
-			end
-			device pci 14.4 on  end # FCH PCI Bridge [1022:780f]
-			device pci 14.5 off end # USB 2
-			device pci 14.6 off end # Gec
-			device pci 14.7 off end # SD
-			device pci 15.0 off end # PCIe 0
-			device pci 15.1 off end # PCIe 1
-			device pci 15.2 off end # PCIe 2
-			device pci 15.3 off end # PCIe 3
-		end	#chip southbridge/amd/agesa/hudson
-
-		chip northbridge/amd/agesa/family15tn
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end
-
-	end	#domain
-end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl
deleted file mode 100644
index c7ab79278e..0000000000
--- a/src/mainboard/lenovo/g505s/dsdt.asl
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "mainboard.h"
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001		/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_SB) */
-	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
-
-	/* Describe the supported Sleep States for this Southbridge */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
-	#include "acpi/sleep.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
-
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
-
-	}   /* End Scope(_SB) */
-
-	Scope(\_SB.PCI0.LIBR) {
-		#include "acpi/ec.asl"
-	}
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/lenovo/g505s/ec.c b/src/mainboard/lenovo/g505s/ec.c
deleted file mode 100644
index 44eb8cf1c7..0000000000
--- a/src/mainboard/lenovo/g505s/ec.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include "ec.h"
-#include <ec/compal/ene932/ec.h>
-
-/* The keyboard matrix tells the EC how the keyboard is wired internally */
-static void set_keyboard_matrix_us(void)
-{
-	ec_kbc_write_cmd(0x59);
-	ec_kbc_write_ib(0xE5);
-}
-
-/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
-static void enter_apm_mode(void)
-{
-	ec_kbc_write_cmd(0x59);
-	ec_kbc_write_ib(0xE9);
-}
-
-void lenovo_g505s_ec_init(void)
-{
-	set_keyboard_matrix_us();
-
-	/*
-	 * The EC has a special "blinking Caps Lock LED" mode which it normally
-	 * enters when it believes the OS is not responding. It occasionally
-	 * disables battery charging when in this mode, although other
-	 * functionality is unaffected. Although the EC starts in APM mode by
-	 * default, it only leaves the "blinking Caps Lock LED" mode after
-	 * receiving the following command.
-	 */
-	enter_apm_mode();
-}
diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h
deleted file mode 100644
index 8b17392e76..0000000000
--- a/src/mainboard/lenovo/g505s/ec.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _MAINBOARD_LENOVO_G505S_EC_H
-#define _MAINBOARD_LENOVO_G505S_EC_H
-
-#include "mainboard.h"
-
-void lenovo_g505s_ec_init(void);
-
-#endif /* _MAINBOARD_LENOVO_G505S_EC_H */
diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c
deleted file mode 100644
index 36caea97de..0000000000
--- a/src/mainboard/lenovo/g505s/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
deleted file mode 100644
index c1ed48652c..0000000000
--- a/src/mainboard/lenovo/g505s/mainboard.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "ec.h"
-
-#include <acpi/acpi.h>
-#include <cpu/x86/smm.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-#include <southbridge/amd/agesa/hudson/smi.h>
-
-static const u8 mainboard_picr_data[0x54] = {
-	0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F
-};
-static const u8 mainboard_intr_data[0x54] = {
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-static void pavilion_cold_boot_init(void)
-{
-	/* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
-	hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW);
-	/* EC is not powered off during S3 sleep */
-	lenovo_g505s_ec_init();
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
-	global_smi_enable();
-
-	if (!acpi_is_wakeup_s3())
-		pavilion_cold_boot_init();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h
deleted file mode 100644
index d4ca524835..0000000000
--- a/src/mainboard/lenovo/g505s/mainboard.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * "The way things are connected" and a few setup options
- */
-
-#ifndef _MAINBOARD_LENOVO_G505S_MAINBOARD_H
-#define _MAINBOARD_LENOVO_G505S_MAINBOARD_H
-
-/* What is connected to GEVENT pins */
-#define EC_SCI_GEVENT		3
-#define EC_LID_GEVENT		22
-#define EC_SMI_GEVENT		23
-#define PCIE_GEVENT		8
-
-/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
- * we make the distinction between GEVENT pin and SCI.
- */
-#define EC_SCI_GPE		EC_SCI_GEVENT
-#define EC_LID_GPE		EC_LID_GEVENT
-#define PME_GPE			0x0b
-#define PCIE_GPE		0x18
-
-/* Enable PS/2 Keyboard and Mouse */
-#define SIO_EC_ENABLE_PS2K
-
-#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */
diff --git a/src/mainboard/lenovo/g505s/smihandler.c b/src/mainboard/lenovo/g505s/smihandler.c
deleted file mode 100644
index fa81b280ee..0000000000
--- a/src/mainboard/lenovo/g505s/smihandler.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * SMI handler -- mostly takes care of SMIs from the EC
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <ec/compal/ene932/ec.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <southbridge/amd/agesa/hudson/smi.h>
-
-#include "ec.h"
-
-#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10)
-
-enum sleep_states {
-	S0 = 0,
-	S1 = 1,
-	S3 = 3,
-	S4 = 4,
-	S5 = 5,
-};
-
-enum ec_smi_event {
-	EC_SMI_EVENT_IDLE = 0x80,
-	EC_SMI_BATTERY_LOW = 0xb3,
-};
-
-/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
-static void ec_enter_apm_mode(void)
-{
-	ec_kbc_write_cmd(0x59);
-	ec_kbc_write_ib(0xE9);
-}
-/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */
-static void ec_enter_acpi_mode(void)
-{
-	ec_kbc_write_cmd(0x59);
-	ec_kbc_write_ib(0xE8);
-}
-
-static uint8_t ec_get_smi_event(void)
-{
-	ec_kbc_write_cmd(0x56);
-	return ec_kbc_read_ob();
-}
-
-static void ec_process_smi(uint8_t src)
-{
-	/* Reading the SMI source satisfies the EC in terms of responding to
-	 * the event, regardless of whether we take an action or not.
-	 */
-
-	switch (src) {
-	case EC_SMI_BATTERY_LOW:
-		printk(BIOS_DEBUG, "Battery low. Shutting down\n");
-		outl(ACPI_PM1_CNT_SLEEP(S5), ACPI_PM1_CNT_BLK);
-		break;
-	default:
-		printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src);
-	}
-}
-
-static void handle_ec_smi(void)
-{
-	uint8_t src;
-
-	while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE)
-		ec_process_smi(src);
-}
-
-static void handle_lid_smi(void)
-{
-	/* Only triggered in non-ACPI mode on lid close. */
-	outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK);
-}
-
-int mainboard_smi_apmc(uint8_t data)
-{
-	switch (data) {
-	case ACPI_SMI_CMD_ENABLE:
-		printk(BIOS_DEBUG, "Enable ACPI mode\n");
-		ec_enter_acpi_mode();
-		hudson_disable_gevent_smi(EC_LID_GEVENT);
-		break;
-	case ACPI_SMI_CMD_DISABLE:
-		printk(BIOS_DEBUG, "Disable ACPI mode\n");
-		ec_enter_apm_mode();
-		hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI,
-					    SMI_LVL_LOW);
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data);
-	}
-	return 0;
-}
-
-void mainboard_smi_gpi(uint32_t gpi_sts)
-{
-	if (gpi_sts & (1 << EC_SMI_GEVENT))
-		handle_ec_smi();
-	if (gpi_sts & (1 << EC_LID_GEVENT))
-		handle_lid_smi();
-}