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| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-03-30 20:12:21 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-11 17:01:46 +0200 |
| commit | 01d75f4172e73fbcdc08ce0a13eaa0efb400ff12 (patch) | |
| tree | 5c6a7c1ab50d5861b772facf7d9c155b51b905fa /src/mainboard/lenovo/g505s | |
| parent | 138b2a03bedb059f7a4064b4ff03d88083774302 (diff) | |
soc/intel/common/block: Add Intel common UART code
Create Intel Common UART driver code. This code does
below UART configuration for bootblock phase.
* Program BAR
* Configure reset register
* Configure clock register
Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/18952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/g505s')
0 files changed, 0 insertions, 0 deletions