mainboard/lenovo/g505s: New port Richland APU A10-5750M

Richland APU A10-5750M
8GB RAM
4MB Flash

Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.

Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 96 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
new file mode 100644
index 0000000000..022e02c9d6
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -0,0 +1,96 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family15rl/root_complex
+
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family15rl
+			device lapic 10 on end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		chip northbridge/amd/agesa/family15rl # CPU side of HT root complex
+
+			chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
+				device pci 0.0 on  end # Root Complex
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
+				device pci 1.1 on  end # Internal Multimedia
+				device pci 2.0 off end
+				device pci 3.0 off end
+				device pci 4.0 on  end # PCIE MINI0
+				device pci 5.0 on  end # PCIE MINI1
+				device pci 6.0 off end #
+				device pci 7.0 off end #
+				device pci 8.0 off end # NB/SB Link P2P bridge ?
+				device pci 9.0 off end #
+			end	#chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
+
+			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 off  end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!)
+				device pci 11.0 on  end # FCH SATA Controller [AHCI mode]
+				device pci 12.0 on  end # FCH USB OHCI Controller
+				device pci 12.2 on  end # FCH USB EHCI Controller
+				device pci 13.0 on  end # FCH USB OHCI Controller
+				device pci 13.2 on  end # FCH USB EHCI Controller
+				device pci 14.0 on      # SMBUS
+					chip drivers/generic/generic #dimm 0
+						device i2c 50 on end # 7-bit SPD address
+					end
+					chip drivers/generic/generic #dimm 1
+						device i2c 51 on end # 7-bit SPD address
+					end
+				end # SM
+				device pci 14.2 on  end # HDA	0x4383
+				device pci 14.3 on  # LPC	0x439d
+					chip ec/compal/ene932
+						# 60/64 KBC
+						device pnp ff.1 on end # dummy address
+					end
+				end
+				device pci 14.2 on  end # FCH Azalia Controller
+				device pci 14.3 on  end # FCH LPC Bridge [1022:780e]
+				device pci 14.4 on  end # FCH PCI Bridge [1022:780f]
+				device pci 14.5 off end # USB 2
+				device pci 14.6 off end # Gec
+				device pci 14.7 off end # SD
+				device pci 15.0 off end # PCIe 0
+				device pci 15.1 off end # PCIe 1
+				device pci 15.2 off end # PCIe 2
+				device pci 15.3 off end # PCIe 3
+				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				register "gpp_configuration" = "4"
+			end	#chip southbridge/amd/hudson
+
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+
+		end	#chip northbridge/amd/agesa/family15rl # CPU side of HT root complex
+	end	#domain
+end	#chip northbridge/amd/agesa/family15rl/root_complex