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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:34:02 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-31 16:30:36 +0000 |
commit | 662cf7f8a6aefbda084a578ce101e3a8943358b2 (patch) | |
tree | c809bef45fc6f2b3839418a9ffcc145859d4613b /src/mainboard/lenovo/g505s/OemCustomize.c | |
parent | 1b526621c9cbfb039b6bfc732ec56d1c4a87e3e9 (diff) |
lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/lenovo/g505s/OemCustomize.c')
-rw-r--r-- | src/mainboard/lenovo/g505s/OemCustomize.c | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 605c7d3f9c..d5a0b51b81 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -140,6 +140,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, }; +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + /*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -156,7 +163,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -188,14 +195,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +209,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -222,7 +221,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} |