mb/lattepanda: Add support for LattePanda Mu

Add initial support for the LattePanda Mu board, which features:
  - Intel Alder Lake-N N100 processor
  - Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory
  - Samsung KLMCG2UCTA-B041, 64GB eMMC storage
  - SO-DIMM 260-pin connector for function expansion

This commit includes:
  - Basic board configuration
  - Memory initialization
  - Essential I/O setup
  - Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file
    from original BIOS
  - BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu
    located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip"

Test Environment:
  - Carrier Board: Lite
  - Payload: mrchromebox/edk2
  - EDK2 Version: uefipayload_202309

Test result
Passed:
  - Windows 11 boot from eMMC
  - Install Ubuntu 24.04 on NVMe SSD
  - Ubuntu 24.04 boot from NVMe SSD
  - USB 3.0/2.0 functionality
  - Realtek RTL8111H-CG-RH Ethernet
  - HDMI Display
    - Audio over HDMI work in Ubuntu 24.04

Known Issues:
  - S3 sleep mode non-functional
  - Power-on after shutdown requires power removal
  - SuperIO UART not detected in Windows 11
  - Audio over HDMI not work in Windows 11
  - Windows 11 BSOD occurs with NVMe SSD installed:
    - Stop code: Machine Check Exception
  - NVMe SSD not working on Windows 11, except when:
    - KDNet Debugging enabled on NIC during boot
    - SSD becomes functional in this scenario

Change-Id: I79696bdd837a221860b32f54629212c3346dca66
Signed-off-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/mainboard/lattepanda/mu/smihandler.c b/src/mainboard/lattepanda/mu/smihandler.c
new file mode 100644
index 0000000000..1de3bb7743
--- /dev/null
+++ b/src/mainboard/lattepanda/mu/smihandler.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <arch/io.h>
+#include <cpu/x86/smm.h>
+#include <intelblocks/smihandler.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define it8613e_index	(0x2e)
+#define EC_DEV		PNP_DEV(it8613e_index, IT8613E_EC)
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	printk(BIOS_DEBUG, "SMI: sleep S%d\n", slp_typ);
+
+	switch (slp_typ) {
+	case ACPI_S3:
+	case ACPI_S4:
+	case ACPI_S5:
+		/* 5VSB_CTRL# Enabled */
+		ite_reg_write(EC_DEV, 0xfa, 2);
+		break;
+	default:
+		break;
+	}
+
+}