diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-05 22:36:14 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-05 22:36:14 +0000 |
| commit | 3a4ed157dcd93f845b92fcea272368bdc41d7a11 (patch) | |
| tree | a38b6e622ebae084de6965d3bc0560f4fbaea5fa /src/mainboard/kontron | |
| parent | e55eb97f4a6c4ce77d0884aaf1adcb0b29e240bf (diff) | |
W83627DHG/W83627EHG fixups for virtual LDNs.
W83627DHG:
- Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
that don't have their "enable" bit in bit 0 of the 0x30 register).
- Fix various I/O masks in the pnp_dev_info[] array as per
datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.
W83627EHG:
- Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
mostly implemented already, though).
- Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.
Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.
include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.
asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.
ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron')
| -rw-r--r-- | src/mainboard/kontron/kt690/devicetree.cb | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index 85df3ae7bf..d509050189 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -83,11 +83,17 @@ chip northbridge/amd/amdk8/root_complex end #device pnp 2e.6 off # SPI #end - device pnp 2e.7 off # GPIO + device pnp 2e.307 off # GPIO 1 end device pnp 2e.8 on # WDTO#, PLED end - device pnp 2e.9 off # GPIO + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 end device pnp 2e.a off # ACPI end |