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authorBenjamin Doron <benjamin.doron00@gmail.com>2020-12-12 22:42:41 +0000
committerNico Huber <nico.h@gmx.de>2020-12-17 20:05:49 +0000
commitac857ca3b166d385caa4faf62b4f1b8fc3b3f2da (patch)
tree7dadb9454b084736d7a931b8cb98c5da5dfe11db /src/mainboard/kontron/bsl6
parenta04400d1aac35299568774304cf9664188570d07 (diff)
soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/kontron/bsl6')
-rw-r--r--src/mainboard/kontron/bsl6/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb
index 6bdfcaf501..8ad785251d 100644
--- a/src/mainboard/kontron/bsl6/devicetree.cb
+++ b/src/mainboard/kontron/bsl6/devicetree.cb
@@ -10,7 +10,6 @@ chip soc/intel/skylake
register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
- register "PmConfigPciClockRun" = "1"
register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
# VR Settings Configuration for 2 Domains