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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-16 14:02:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 19:03:22 +0000 |
| commit | 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 (patch) | |
| tree | 4562bd212e40d0832fa893935d85a06d82f8a897 /src/mainboard/kontron/986lcd-m | |
| parent | 146c09823333c52e8bbca98465ccc8512ec1daa2 (diff) | |
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c940536a03..0981fe8989 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -18,7 +18,6 @@ #include <delay.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -241,12 +240,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -259,9 +257,6 @@ void mainboard_romstage_entry(unsigned long bist) /* Set up the console */ console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); |