diff options
| author | Patrick Georgi <patrick.georgi@secunet.com> | 2011-01-27 07:39:38 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2011-01-27 07:39:38 +0000 |
| commit | a470019b7a19e164b5dc93b1d541dc4158edbeda (patch) | |
| tree | 48156b3fb7f795cbe3241f787b642460aa03a29d /src/mainboard/kontron/986lcd-m/romstage.c | |
| parent | a5c949eff288af3eb4caffec57a3724c497150de (diff) | |
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/romstage.c')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 5d773ce636..925c93efe8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -58,12 +58,16 @@ void setup_ich7_gpios(void) static void ich7_enable_lpc(void) { + int lpt_en = 0; + if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); // Enable HWM at 0xa00 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); // COM3 decode |