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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-11 10:26:11 +0000 |
| commit | 93d215cb05a05464fef14f26f638341da2ce3d59 (patch) | |
| tree | 9e33a2efb7e6c5a0cb6e90d9f186e73074718b28 /src/mainboard/jetway | |
| parent | b4d960b65aa126d4534189672322ec62dcd87bde (diff) | |
soc/intel/cannonlake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/jetway')
0 files changed, 0 insertions, 0 deletions