diff options
| author | Martin Roth <gaumless@gmail.com> | 2014-04-25 15:09:27 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2014-05-09 21:36:12 +0200 |
| commit | 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c (patch) | |
| tree | 164e0f702179302236d8477d889804e405f143a2 /src/mainboard/jetway | |
| parent | a6427161c20bfb8319208dbbd08697a530a3839e (diff) | |
cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.
These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda
Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/jetway')
0 files changed, 0 insertions, 0 deletions