diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 13:38:47 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:03:43 +0000 |
| commit | fe67951fa763ee9a2c7056167e039bc72a8ebc29 (patch) | |
| tree | 2117a766d0f05323d7d5a5c192b24cf2914f8a92 /src/mainboard/jetway/pa78vm5 | |
| parent | cd5f2b500def9826f9639514c7f78b54633787e0 (diff) | |
mb/jetway: Get rid of whitespace before tab
Change-Id: Icc7d7fee38e41f4bfda685fd42bf504a788b440c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/jetway/pa78vm5')
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/dsdt.asl | 38 |
2 files changed, 21 insertions, 21 deletions
diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 783e4ae9f3..79915ac26b 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 7b8b8c8145..1b9d31c44d 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1520,7 +1520,7 @@ DefinitionBlock ( ) Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1634,7 +1634,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ |