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| author | Hannah Williams <hannah.williams@intel.com> | 2018-04-14 23:04:34 -0700 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-04-16 05:04:35 +0000 |
| commit | 57d8ccb5f0c7733656ea2aeae4e2cc6feb998725 (patch) | |
| tree | 318fa3ea909902ddd880394368c133b47f634b45 /src/mainboard/jetway/pa78vm5/cmos.layout | |
| parent | 0c557cd983e021b1675fb1688784652d4815f0ba (diff) | |
soc/intel/apollolake: Fix CPU address bits
APL and GLK have 39 address bits
Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/jetway/pa78vm5/cmos.layout')
0 files changed, 0 insertions, 0 deletions