diff options
| author | Mike Banon <mikebdp2@gmail.com> | 2020-02-13 16:16:01 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 13:54:59 +0000 |
| commit | c896df7f158cf759906f4f164330fb552bbe0fec (patch) | |
| tree | 63ec22c010467c201412df71447e1c7219668551 /src/mainboard/jetway/nf81-t56n-lf/romstage.c | |
| parent | e3229a5192a84c04a4d1f0307d8cfb5e864b7ff3 (diff) | |
mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/romstage.c')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/romstage.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c deleted file mode 100644 index 5e61bddfcc..0000000000 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f71869ad/f71869ad.h> -#include <sb_cimx.h> - -/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ -#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - sb_Poweron_Init(); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} |