diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-01-25 07:40:39 +1100 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-02-16 04:51:31 +0100 |
| commit | 4726a87c9a615dc26733cd799f8c4b78670f9ae7 (patch) | |
| tree | ded9170a01760ff7a7bd969b900853af4d67ae22 /src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | |
| parent | 80865c961915dd2ca866c8e59874098a6af3dbcb (diff) | |
Jetway NF81-T56N-LF [1/2]: create board by forking AMD Persimmon
Step 1: copy all files unmodified from Persimmon. This makes it much
easier later to see how the two boards actually and deliberately differ
when porting bugfixes from one to the other.
Change-Id: I23e223049ed1c69e320e6b31efe4266bfeb97207
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/dsdt.asl')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl new file mode 100644 index 0000000000..f7c7bb2de3 --- /dev/null +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + #include "acpi/mainboard.asl" + + #include <cpu/amd/agesa/family14/acpi/cpu.asl> + + #include "acpi/routing.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + Device(PCI0) { + + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/cimx/sb800/acpi/fch.asl> + + } + } /* End Scope(_SB) */ + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + #include "acpi/gpe.asl" + #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> + #include "acpi/thermal.asl" +} +/* End of ASL file */ |