diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-04-24 02:58:11 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-08 12:10:37 +0200 |
| commit | dd2e8c35fb368316b51d969d046696a017f09d25 (patch) | |
| tree | 77e70b316e26114ed1a361f6e784937d65db4c0a /src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | |
| parent | 708be1a45356b33eaf5f287e529a99fb856736af (diff) | |
superio/fintek/f71869ad: Configure multi-func reg in devicetree
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.
Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.
Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/devicetree.cb')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 6c26f75fb4..1c8853dd21 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, |