diff options
author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-04-10 19:12:28 +1000 |
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committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-15 05:16:21 +0200 |
commit | feebd86ad2fe78955fda852103a8363a2da0cf59 (patch) | |
tree | 9794c3ad47079b37c8f2a270ef54f93cc50eaa3b /src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | |
parent | c12db59bced7b54dc9f55bbb06716a46875b211a (diff) |
mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Keep under 80 colums and Doxygen'ify inline documentation somewhat.
Strip some whitespace bulk while here and refactor a little as to line
wrap.
Additionally, following the reasoning of:
0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
remove some fluff from buildOpts.c
Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5481
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h')
-rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 88 |
1 files changed, 52 insertions, 36 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index 20877f10e2..dd6f7d7c7d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,46 +24,61 @@ #include <vendorcode/amd/agesa/f14/AGESA.h> #include <vendorcode/amd/agesa/f14/Lib/amdlib.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ |