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authorHannah Williams <hannah.williams@intel.com>2017-05-13 16:18:02 -0700
committerAaron Durbin <adurbin@chromium.org>2017-05-22 21:37:09 +0200
commitf714965e8deca6e092f0a416d2c4c752a225e39e (patch)
tree3b4eaec6f54cd48dda5ee2c6affd5781c0fa44cf /src/mainboard/jetway/j7f4k1g2e
parent3038e9bd08222bc7bb4fa3988b66c31ee9e5daff (diff)
soc/intel/common/block/uart: Add GLK UART pci ids
Change-Id: I08dd7a8c0d42d4ec7c6ff65a82553fe1efbcc424 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19687 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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