This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 395 insertions, 395 deletions

diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb
index faa294924f..54a66c7939 100644
--- a/src/mainboard/iwill/dk8_htx/Config.lb
+++ b/src/mainboard/iwill/dk8_htx/Config.lb
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/failovercalculation.lb
 
 arch i386 end 
@@ -15,25 +15,25 @@ driver mainboard.o
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE 
+if CONFIG_HAVE_MP_TABLE 
 	object mptable.o 
 end
 
-if HAVE_PIRQ_TABLE 
+if CONFIG_HAVE_PIRQ_TABLE 
 	object irq_tables.o 
 end
 
-#if HAVE_ACPI_TABLES
+#if CONFIG_HAVE_ACPI_TABLES
 #       object acpi_tables.o
 #       object fadt.o
-#       if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_SB_HT_CHAIN_ON_BUS0
 #               object dsdt_bus0.o
 #       else
 #               object dsdt.o
 #       end
 #       object ssdt.o
-#       if ACPI_SSDTX_NUM
-#                if SB_HT_CHAIN_ON_BUS0
+#       if CONFIG_ACPI_SSDTX_NUM
+#                if CONFIG_SB_HT_CHAIN_ON_BUS0
 #                 object ssdt2_bus0.o
 #                else
 #                 object ssdt2.o
@@ -41,43 +41,43 @@ end
 #       end
 #end
 
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
         object acpi_tables.o
         object fadt.o
 	makerule dsdt.c
-		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
+		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
 		action  "mv dsdt_lb.hex dsdt.c"
 	end
         object ./dsdt.o
 
 	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
 	
-        if ACPI_SSDTX_NUM
+        if CONFIG_ACPI_SSDTX_NUM
             makerule ssdt2.c
-                        depends "$(MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
+                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
             makerule ssdt3.c
-                        depends "$(MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
+                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
                         action  "mv pci3.hex ssdt3.c"
             end
             object ./ssdt3.o
             makerule ssdt4.c
-                        depends "$(MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
+                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
                         action  "mv pci4.hex ssdt4.c"
             end
             object ./ssdt4.o
             makerule ssdt5.c
-                        depends "$(MAINBOARD)/dx/pci5.asl"
-                        action  "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
+                        depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
+                        action  "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
                         action  "mv pci5.hex ssdt5.c"
             end
@@ -88,27 +88,27 @@ end
 	if CONFIG_USE_INIT
 		# compile cache_as_ram.c to auto.o
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		end
 
 	else   
 		#compile cache_as_ram.c to auto.inc 
 		makerule ./cache_as_ram_auto.inc
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 		end
 
 	end
 
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
 	makerule ./apc_auto.o
-		depends "$(MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
 	end
 	ldscript /arch/i386/init/ldscript_apc.lb
     end
@@ -118,13 +118,13 @@ end
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
 
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 	mainboardinit cpu/x86/16bit/entry16.inc
 	ldscript /cpu/x86/16bit/entry16.lds
     end
@@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT
 	ldscript /cpu/x86/32bit/reset32.lds 
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
     else
@@ -176,12 +176,12 @@ ldscript /arch/i386/lib/id.lds
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+    if CONFIG_USE_FAILOVER_IMAGE
 		ldscript /arch/i386/lib/failover_failover.lds
     end
 else
-    if USE_FALLBACK_IMAGE
+    if CONFIG_USE_FALLBACK_IMAGE
 		ldscript /arch/i386/lib/failover.lds
     end
 end
diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb
index 305d8026bc..1f08f6a603 100644
--- a/src/mainboard/iwill/dk8_htx/Options.lb
+++ b/src/mainboard/iwill/dk8_htx/Options.lb
@@ -1,85 +1,85 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
-
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
 
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
 
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
@@ -87,9 +87,9 @@ uses CONFIG_LB_MEM_TOPK
 
 uses CONFIG_AP_CODE_IN_CAR
 
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
 
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
 
 uses CONFIG_USE_PRINTK_IN_CAR
 
@@ -98,20 +98,20 @@ uses CONFIG_USE_PRINTK_IN_CAR
 ###
 
 ##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
 ##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-8K
-default FALLBACK_SIZE=0x3e000
+default CONFIG_FALLBACK_SIZE=0x3e000
 #FAILOVER: 8K
-default FAILOVER_SIZE=0x02000
+default CONFIG_FAILOVER_SIZE=0x02000
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -119,42 +119,42 @@ default CONFIG_LB_MEM_TOPK=2048
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_ACPI_TABLES=1
 ## extra SSDT num
-default ACPI_SSDTX_NUM=3
+default CONFIG_ACPI_SSDTX_NUM=3
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -165,41 +165,41 @@ default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=2
 default CONFIG_LOGICAL_CPUS=1
 
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
 
 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
 #2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
 #1G
-#default HW_MEM_HOLE_SIZEK=0x100000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
 #512M
-default HW_MEM_HOLE_SIZEK=0x80000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
 
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
 
 #Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
 
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
 #HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0xa
+default CONFIG_HT_CHAIN_UNITID_BASE=0xa
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x6
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
 
 #make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
 
 #only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 
 #allow capable device use that above 4G
 #default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -207,18 +207,18 @@ default SB_HT_CHAIN_ON_BUS0=2
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc4000
-default DCACHE_RAM_SIZE=0x0c000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc4000
+default CONFIG_DCACHE_RAM_SIZE=0x0c000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
 ##
 ## for rev F training on AP purpose
 ##
 #default CONFIG_AP_CODE_IN_CAR=1
-#default MEM_TRAIN_SEQ=1
-#default WAIT_BEFORE_CPUS_INIT=1
+#default CONFIG_MEM_TRAIN_SEQ=1
+#default CONFIG_WAIT_BEFORE_CPUS_INIT=1
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -228,37 +228,37 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="dk8_htx"
-default MAINBOARD_VENDOR="IWILL"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+default CONFIG_MAINBOARD_PART_NUMBER="dk8_htx"
+default CONFIG_MAINBOARD_VENDOR="IWILL"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
 
 ##
 ## Load the payload from the ROM
@@ -272,8 +272,8 @@ default CONFIG_ROM_PAYLOAD = 1
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -289,21 +289,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -315,17 +315,17 @@ default TTYS0_LCS=0x3
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c
index c382e3e298..53822bd9d6 100644
--- a/src/mainboard/iwill/dk8_htx/acpi_tables.c
+++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c
@@ -40,7 +40,7 @@ static void dump_mem(unsigned start, unsigned end)
 
 extern unsigned char AmlCode[];
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 extern unsigned char AmlCode_ssdt2[];
 extern unsigned char AmlCode_ssdt3[];
 extern unsigned char AmlCode_ssdt4[];
@@ -266,7 +266,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += ssdt->length;
 	acpi_add_table(rsdt, ssdt);
 
-#if ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
         //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
 
diff --git a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
index cb292bde7b..72c1b86b63 100644
--- a/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index d49333c261..ae3b25dcb7 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -109,7 +109,7 @@ void get_bus_conf(void)
         dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
         if (dev) {
                 m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //		printk_debug("bus_isa=%d\n",bus_isa);
@@ -132,7 +132,7 @@ void get_bus_conf(void)
         dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
         if (dev) {
                 m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
                 m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                 m->bus_isa++;
 //              printk_debug("bus_isa=%d\n",bus_isa);
diff --git a/src/mainboard/iwill/dk8s2/Config.lb b/src/mainboard/iwill/dk8s2/Config.lb
index bf1806b440..8f34a30aa3 100644
--- a/src/mainboard/iwill/dk8s2/Config.lb
+++ b/src/mainboard/iwill/dk8s2/Config.lb
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,8 +13,8 @@ arch i386 end
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 ## ATI Rage XL framebuffering graphics driver
@@ -23,15 +23,15 @@ dir /drivers/ati/ragexl
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -41,7 +41,7 @@ end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -59,7 +59,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -83,7 +83,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 
diff --git a/src/mainboard/iwill/dk8s2/Options.lb b/src/mainboard/iwill/dk8s2/Options.lb
index 6c0fb018c3..e9a3bafc34 100644
--- a/src/mainboard/iwill/dk8s2/Options.lb
+++ b/src/mainboard/iwill/dk8s2/Options.lb
@@ -1,106 +1,106 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE=524288
 
 ###
 ### Build options
 ###
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -118,46 +118,46 @@ default CONFIG_IOAPIC=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
+default CONFIG_MAINBOARD_VENDOR="ARIMA"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -171,8 +171,8 @@ default CONFIG_ROM_PAYLOAD = 1
 ##
 ## The default compiler
 ##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
+#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+#default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -189,21 +189,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -215,17 +215,17 @@ default TTYS0_LCS=0x3
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #
diff --git a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
index 6716a55825..51617ab0ce 100644
--- a/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0
diff --git a/src/mainboard/iwill/dk8x/Config.lb b/src/mainboard/iwill/dk8x/Config.lb
index 216cceb172..7e2dd6dbf5 100644
--- a/src/mainboard/iwill/dk8x/Config.lb
+++ b/src/mainboard/iwill/dk8x/Config.lb
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 ##
@@ -13,22 +13,22 @@ arch i386 end
 ##
 
 driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 if CONFIG_USE_INIT
 
 makerule ./auto.o
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
 end
 
 else    
                 
 makerule ./auto.inc
-        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 end
@@ -38,7 +38,7 @@ end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
         ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -56,7 +56,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
 	mainboardinit cpu/x86/16bit/reset16.inc 
 	ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -80,7 +80,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
 end
 
diff --git a/src/mainboard/iwill/dk8x/Options.lb b/src/mainboard/iwill/dk8x/Options.lb
index a515945180..5b6cd23ed4 100644
--- a/src/mainboard/iwill/dk8x/Options.lb
+++ b/src/mainboard/iwill/dk8x/Options.lb
@@ -1,106 +1,106 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
 uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
 uses CC
-uses HOSTCC
-uses OBJCOPY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE=524288
 
 ###
 ### Build options
 ###
 
 ##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
 
 ##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
 
 ##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
 
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
 
 ##
 ## Build code to export an x86 MP table
 ## Useful for specifying IRQ routing values
 ##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
 
 ##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default coreboot cmos range off of AMD RTC registers
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
 
 ##
 ## Build code for SMP support
@@ -118,45 +118,45 @@ default CONFIG_IOAPIC=1
 ##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
 default CONFIG_USE_INIT=0
  
 ##
 ## Clean up the motherboard id strings
 ##
-#default MAINBOARD_PART_NUMBER="HDAMA"
-#default MAINBOARD_VENDOR="ARIMA"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+#default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
+#default CONFIG_MAINBOARD_VENDOR="ARIMA"
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
 
 ###
 ### coreboot layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
 
 ##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
 
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
 
 ##
 ## Only use the option table in a normal image
 ##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
 
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -170,8 +170,8 @@ default CONFIG_ROM_PAYLOAD = 1
 ##
 ## The default compiler
 ##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
+#default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+#default CONFIG_HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -188,21 +188,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
 default CONFIG_CONSOLE_SERIAL8250=1
 
 ## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
 
 # Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
 
 # Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
 
 ##
 ### Select the coreboot loglevel
@@ -214,17 +214,17 @@ default TTYS0_LCS=0x3
 ## WARNING    5   warning conditions               
 ## NOTICE     6   normal but significant condition 
 ## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
+## CONFIG_DEBUG      8   debug-level messages             
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
 ### End Options.lb
 #
diff --git a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
index 6716a55825..51617ab0ce 100644
--- a/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
+++ b/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -34,7 +34,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
@@ -48,7 +48,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -132,7 +132,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -177,7 +177,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
                 );
 
  fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
         __asm__ volatile ("jmp __fallback_image"
                 : /* outputs */
                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -191,21 +191,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
-    #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1 
+    #if CONFIG_USE_FAILOVER_IMAGE==1
 	failover_process(bist, cpu_init_detectedx);	
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
-    #if USE_FALLBACK_IMAGE == 1
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);	
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
 }
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -221,7 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	};
 
-	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset; int i;
         unsigned bsp_apicid = 0;
@@ -230,7 +230,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
- 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
@@ -243,7 +243,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
 #endif
 	setup_coherent_ht_domain(); // routing table and start other core0
diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c
index 6322c3df21..1f35cbaef2 100644
--- a/src/mainboard/iwill/dk8x/irq_tables.c
+++ b/src/mainboard/iwill/dk8x/irq_tables.c
@@ -18,7 +18,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE,		/* u32 signature */
 	PIRQ_VERSION,		/* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT 
+	32+16*CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT 
 				 * devices on the bus */
 	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
 	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */