diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 00:04:22 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-31 03:41:11 +0000 |
| commit | 1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch) | |
| tree | bf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/iwill | |
| parent | f054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff) | |
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/iwill')
37 files changed, 0 insertions, 3187 deletions
diff --git a/src/mainboard/iwill/Kconfig b/src/mainboard/iwill/Kconfig deleted file mode 100644 index 75fa626b60..0000000000 --- a/src/mainboard/iwill/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if VENDOR_IWILL - -choice - prompt "Mainboard model" - -source "src/mainboard/iwill/*/Kconfig.name" - -endchoice - -source "src/mainboard/iwill/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "IWILL" - -endif # VENDOR_IWILL diff --git a/src/mainboard/iwill/Kconfig.name b/src/mainboard/iwill/Kconfig.name deleted file mode 100644 index 026608bec6..0000000000 --- a/src/mainboard/iwill/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_IWILL - bool "IWILL" diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig deleted file mode 100644 index 929f47f540..0000000000 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -if BOARD_IWILL_DK8_HTX - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_940 - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_AMD_AMD8111 - select SOUTHBRIDGE_AMD_AMD8131 - select HT_CHAIN_DISTRIBUTE - select SUPERIO_WINBOND_W83627HF - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select LIFT_BSP_APIC_ID - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_512 - select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT - -config MAINBOARD_DIR - string - default iwill/dk8_htx - -config APIC_ID_OFFSET - hex - default 0x10 - -config MAINBOARD_PART_NUMBER - string - default "DK8-HTX" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x6 - -config HT_CHAIN_UNITID_BASE - hex - default 0xa - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_IWILL_DK8_HTX diff --git a/src/mainboard/iwill/dk8_htx/Kconfig.name b/src/mainboard/iwill/dk8_htx/Kconfig.name deleted file mode 100644 index 8d81fc199d..0000000000 --- a/src/mainboard/iwill/dk8_htx/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_IWILL_DK8_HTX - bool "DK8-HTX" diff --git a/src/mainboard/iwill/dk8_htx/Makefile.inc b/src/mainboard/iwill/dk8_htx/Makefile.inc deleted file mode 100644 index e826e8153a..0000000000 --- a/src/mainboard/iwill/dk8_htx/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -$(eval $(call asl_template,ssdt2)) -$(eval $(call asl_template,ssdt3)) -$(eval $(call asl_template,ssdt4)) -$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl deleted file mode 100644 index df722f8862..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright 2005 AMD - */ -//AMD8111 - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} - }) - - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) - // Update the Device Number according to SBDN - Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) - - Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { - Return (PICM) - } - Else { - Return (APIC) - } - } - - Device (SBC3) - { - /* ACPI smbus it should be 0x00040003 if 8131 present */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) - } - OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) - Field (PIRQ, ByteAcc, Lock, Preserve) - { - PIBA, 8, - PIDC, 8 - } -/* - OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) - Field (TS3_, DWordAcc, NoLock, Preserve) - { - PTS3, 16 - } -*/ - } - - Device (HPET) - { - Name (HPT, 0x00) - Name (_HID, EisaId ("PNP0103")) - Name (_UID, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) - }) - Return (BUF0) - } - } - - #include "amd8111_pic.asl" - - #include "amd8111_isa.asl" - - Device (TP2P) - { - /* 8111 P2P and it should 0x00030000 when 8131 present*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x08, 0x03 }) } - Else { Return (Package (0x02) { 0x08, 0x01 }) } - } - - Device (USB0) - { - Name (_ADR, 0x00000000) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Device (USB1) - { - Name (_ADR, 0x00000001) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Name (APIC, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } - }) - - Name (PICM, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } - }) - - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl deleted file mode 100644 index 6054b53d5e..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ /dev/null @@ -1,178 +0,0 @@ -#include <arch/ioapic.h> -#include <cpu/x86/lapic_def.h> - -/* - * Copyright 2005 AMD - */ -//AMD8111 isa - - Device (ISA) - { - /* lpc 0x00040000 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) - } - - OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers - Field (PIRY, ByteAcc, NoLock, Preserve) - { - Z000, 2, // Parallel Port Range - , 1, - ECP, 1, // ECP Enable - FDC1, 1, // Floppy Drive Controller 1 - FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), - Z001, 3, // Serial Port A Range - SAEN, 1, // Serial Post A Enabled - Z002, 3, // Serial Port B Range - SBEN, 1 // Serial Post B Enabled - } - - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) - IRQ (Edge, ActiveHigh, Exclusive) {2} - }) - } - - Device (DMA1) - { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) - IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) - IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer16) {4} - }) - } - - Device (TMR) - { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) - IRQ (Edge, ActiveHigh, Exclusive) {0} - }) - } - - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) - IRQ (Edge, ActiveHigh, Exclusive) {8} - }) - } - - Device (SPKR) - { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) - }) - } - - Device (COPR) - { - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) - IRQ (Edge, ActiveHigh, Exclusive) {13} - }) - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x00) - Name (SYR1, ResourceTemplate () - { - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) - IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) - IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) - IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - }) - Method (_CRS, 0, NotSerialized) - { - Return (SYR1) - } - } - - Device (MEM) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF - Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - }) - // Read the Video Memory length - CreateDWordField (BUF0, 0x14, CLEN) - CreateDWordField (BUF0, 0x10, CBAS) - - ShiftLeft (VGA1, 0x09, Local0) - Store (Local0, CLEN) - - Return (BUF0) - } - } - - Device (PS2M) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQNoFlags () {12} - }) - Method (_STA, 0, NotSerialized) - { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { Return (0x0F) } - Else { Return (0x00) } - } - } - - Device (PS2K) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } - #include "superio.asl" - - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl deleted file mode 100644 index fd1df7d034..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright 2005 AMD - */ -//AMD8111 pic LNKA B C D - - Device (LNKA) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { // Routing enable - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA) - Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKB) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA) - ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKC) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC) - Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) - } - } - - Device (LNKD) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) - { - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC) - ShiftLeft (Local1, 0x04, Local1) - Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC) - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl deleted file mode 100644 index 6d93e02048..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2005 AMD - */ - - Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x14) - { - // Slot 3 - PIRQ BCDA ---- verified - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - - //Slot 4 - PIRQ CDAB ---- verified - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, - - //Onboard NIC 1 - PIRQ DABC - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, - - // NIC 2 - PIRQ ABCD -- verified - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, - - //SERIAL ATA - PIRQ BCDA - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } - }) - Name (PICM, Package (0x14) - { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ CDAB -- verfied - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl deleted file mode 100644 index 6eb95ec724..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2005 AMD - */ - - Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl deleted file mode 100644 index 9c0629f779..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2005 AMD - */ - - Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { - // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl deleted file mode 100644 index 995aa10475..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl +++ /dev/null @@ -1,28 +0,0 @@ -// AMD8151 - Device (AGPB) - { - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl deleted file mode 100644 index 7301fef998..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2006 AMD - */ - - Device (HTXA) - { - /* HTX */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (\_S3)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - } diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl deleted file mode 100644 index 2fd3b09de4..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/pci0_hc.asl +++ /dev/null @@ -1,2 +0,0 @@ - #include "amd8111.asl" //real SB at first - #include "amd8131.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl deleted file mode 100644 index fd3ad2c3e3..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/pci2_hc.asl +++ /dev/null @@ -1 +0,0 @@ - #include "amd8132_2.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl deleted file mode 100644 index 070ebe5286..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/pci3_hc.asl +++ /dev/null @@ -1 +0,0 @@ - #include "amd8151.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl deleted file mode 100644 index bd3f70ea0f..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/pci4_hc.asl +++ /dev/null @@ -1 +0,0 @@ - #include "amd8131_2.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl b/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl deleted file mode 100644 index f7f0a7dbad..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/pci5_hc.asl +++ /dev/null @@ -1 +0,0 @@ - #include "htx_no_ioapic.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi/superio.asl b/src/mainboard/iwill/dk8_htx/acpi/superio.asl deleted file mode 100644 index 83ee58253d..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -// #include "w83627hf.asl" diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c deleted file mode 100644 index 957be79ca3..0000000000 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Island Aruma ACPI support - * written by Stefan Reinauer <stepan@openbios.org> - * (C) 2005 Stefan Reinauer - * - * - * Copyright 2005 AMD - * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "northbridge/amd/amdk8/acpi.h" -#include "mb_sysconf.h" -#include "mainboard.h" -#include <cbfs.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - unsigned int gsi_base = 0x18; - - struct mb_sysconf_t *m; - - get_bus_conf(); - - m = sysconf.mb; - - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write 8111 IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, - IO_APIC_ADDR, 0); - - /* Write all 8131 IOAPICs */ - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); - gsi_base+=4; - - } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); - gsi_base+=4; - } - } - - int i; - int j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { - unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 - - switch (sysconf.hcid[i]) { - case 1: - d = 7; - break; - case 3: - d = 4; - break; - } - switch (sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - - } - - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) - current, 0, 0, 2, 5 ); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high*/ - - - /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); - /* 1: LINT1 connect to NMI */ - - - return current; -} - -unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long start, - acpi_rsdp_t *rsdp) -{ - unsigned long current; - acpi_header_t *ssdtx; - const void *p; - size_t p_size; - - int i; - - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn - - /* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); - current = start; - - //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table - - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink - const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; - uint8_t c; - if(i < 7) { - c = (uint8_t) ('4' + i - 1); - } - else { - c = (uint8_t) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { - case 1: //8132 - file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; - break; - case 2: //8151 - file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; - break; - case 3: //8131 - file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; - break; - default: - //HTX no io apic - file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; - break; - } - p = cbfs_boot_map_with_leak( - file_name, - CBFS_TYPE_RAW, &p_size); - if (!p || p_size < sizeof(acpi_header_t)) - continue; - - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); - acpi_add_table(rsdp,ssdtx); - } - - return current; -} diff --git a/src/mainboard/iwill/dk8_htx/board_info.txt b/src/mainboard/iwill/dk8_htx/board_info.txt deleted file mode 100644 index 4211c8d532..0000000000 --- a/src/mainboard/iwill/dk8_htx/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Category: server -Board URL: http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 -Flashrom support: y diff --git a/src/mainboard/iwill/dk8_htx/cmos.layout b/src/mainboard/iwill/dk8_htx/cmos.layout deleted file mode 100644 index 56ed652b97..0000000000 --- a/src/mainboard/iwill/dk8_htx/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb deleted file mode 100644 index c49c97a048..0000000000 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ /dev/null @@ -1,117 +0,0 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 - io 0x07 = 0x08ff - io 0x30 = 0x01ff - io 0x2b = 0xd0ff - io 0xf0 = 0xef16 - end - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - - end #domain -end diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl deleted file mode 100644 index e1e6341a72..0000000000 --- a/src/mainboard/iwill/dk8_htx/dsdt.asl +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright 2005 AMD - */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) -{ - Scope (_PR) - { - Processor (CPU0, 0x00, 0x0000C010, 0x06) {} - Processor (CPU1, 0x01, 0x00000000, 0x00) {} - Processor (CPU2, 0x02, 0x00000000, 0x00) {} - Processor (CPU3, 0x03, 0x00000000, 0x00) {} - - } - - Method (FWSO, 0, NotSerialized) { } - - Scope (_SB) - { - Device (PCI0) - { - /* BUS0 root bus */ - - External (BUSN) - External (MMIO) - External (PCIO) - External (SBLK) - External (TOM1) - External (HCLK) - External (SBDN) - External (HCDN) - External (CBST) - - - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - \_SB.OSVR () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) - Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) - Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci0_hc.asl" - - } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.CBST) - } - Name (_BBN, 0x00) - } - - - } - - Scope (_GPE) - { - Method (_L08, 0, NotSerialized) - { - Notify (\_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (\_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (\_SB.PCI0.PG0A, 0x02) - } - } - - Method (_PTS, 1, NotSerialized) - { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) - } -/* - Method (_WAK, 1, NotSerialized) - { - Or (Arg0, 0xE0, Local0) - Store (Local0, DBG1) - } -*/ - Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode - Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method - { - Store (Arg0, PICF) - } - - OperationRegion (DEBG, SystemIO, 0x80, 0x01) - Field (DEBG, ByteAcc, Lock, Preserve) - { - DBG1, 8 - } - - OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) - Field (EXTM, WordAcc, Lock, Preserve) - { - AMEM, 32 - } - - OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) - Field (VGAM, ByteAcc, Lock, Preserve) - { - VGA1, 8 - } - - OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) - Field (GRAM, ByteAcc, Lock, Preserve) - { - Offset (0x10), - FLG0, 8 - } - - OperationRegion (GSTS, SystemIO, 0xC028, 0x02) - Field (GSTS, ByteAcc, NoLock, Preserve) - { - , 4, - IRQR, 1 - } - - OperationRegion (Z007, SystemIO, 0x21, 0x01) - Field (Z007, ByteAcc, NoLock, Preserve) - { - Z008, 8 - } - - OperationRegion (Z009, SystemIO, 0xA1, 0x01) - Field (Z009, ByteAcc, NoLock, Preserve) - { - Z00A, 8 - } - - #include "northbridge/amd/amdk8/util.asl" - -} diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c deleted file mode 100644 index 5a7c2a789f..0000000000 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org> - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> - -extern unsigned pm_base; /* pm_base should be set in sb ACPI */ - -void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ - - acpi_header_t *header=&(fadt->header); - - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - - /* Prepare the header */ - memset((void *)fadt,0,sizeof(acpi_fadt_t)); - memcpy(header->signature,"FACP",4); - header->length = 244; - header->revision = 3; - memcpy(header->oem_id,OEM_ID,6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id,ASLC,4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl=(u32)facs; - fadt->dsdt= (u32)dsdt; - // 3=Workstation, 4=Enterprise Server, 7=Performance Server - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - // disable system management mode by setting to 0: - fadt->smi_cmd = 0;//pm_base+0x2f; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - fadt->pm1a_evt_blk = pm_base; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = pm_base+0x04; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->gpe1_blk_len = 8; - fadt->gpe1_base = 16; - - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0; // 0x7d these have to be - fadt->mon_alrm = 0; // 0x7e added to cmos.layout - fadt->century = 0; // 0x7f to make rtc alrm work - fadt->iapc_boot_arch = 0x3; // See table 5-11 - fadt->flags = 0x25; - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pm_base; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pm_base+4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pm_base+0x08; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pm_base+0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 64; - fadt->x_gpe1_blk.bit_offset = 16; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = pm_base+0xb0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); - -} diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c deleted file mode 100644 index 1121fb3689..0000000000 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ /dev/null @@ -1,217 +0,0 @@ -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#include <cpu/amd/multicore.h> - -#include <cpu/amd/amdk8_sysconf.h> - -#include <stdlib.h> -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, // SB chain m - 0x0000000, // HTX - 0x0000100, // co processor on socket 1 -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; - -static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; - -static unsigned get_bus_conf_done = 0; - -static unsigned get_hcid(unsigned i) -{ - unsigned id = 0; - - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - - unsigned devn = sysconf.hcdn[i] & 0xff; - - struct device *dev; - - dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - - switch (dev->device) { - case 0x7458: //8132 - id = 1; - break; - case 0x7454: //8151 - id = 2; - break; - case 0x7450: //8131 - id = 3; - break; - } - - // we may need more way to find out hcid: subsystem id? GPIO read ? - - // we need use id for 1. bus num, 2. mptable, 3. ACPI table - - return id; -} - -void get_bus_conf(void) -{ - - unsigned apicid_base; - - struct device *dev; - int i, j; - struct mb_sysconf_t *m; - - if (get_bus_conf_done == 1) - return; //do it only once - - get_bus_conf_done = 1; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - m->sbdn3 = sysconf.hcdn[0] & 0xff; - - m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff; - m->bus_8111_0 = m->bus_8132_0; - - /* 8111 */ - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn, 0)); - if (dev) { - m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8111_0, sysconf.sbdn); - } - - /* 8132-1 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 0)); - if (dev) { - m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3); - } - - /* 8132-2 */ - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3 + 1, 0)); - if (dev) { - m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3 + 1); - } - - /* HT chain 1 */ - j = 0; - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - - // check hcid type here - sysconf.hcid[i] = get_hcid(i); - - switch (sysconf.hcid[i]) { - - case 1: //8132 - case 3: //8131 - - m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - - m->sbdn3a[j] = sysconf.hcdn[i] & 0xff; - - /* 8132-1 */ - dev = - dev_find_slot(m->bus_8132a[j][0], - PCI_DEVFN(m->sbdn3a[j], 0)); - if (dev) { - m->bus_8132a[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j]); - } - - /* 8132-2 */ - dev = - dev_find_slot(m->bus_8132a[j][0], - PCI_DEVFN(m->sbdn3a[j] + 1, 0)); - if (dev) { - m->bus_8132a[j][2] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j] + 1); - } - - break; - - case 2: //8151 - - m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff; - m->sbdn5[j] = sysconf.hcdn[i] & 0xff; - /* 8151 */ - dev = - dev_find_slot(m->bus_8151[j][0], - PCI_DEVFN(m->sbdn5[j] + 1, 0)); - - if (dev) { - m->bus_8151[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8151[j][0], m->sbdn5[j] + 1); - } - - break; - } - - j++; - } - -/*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(3); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_8111 = apicid_base + 0; - m->apicid_8132_1 = apicid_base + 1; - m->apicid_8132_2 = apicid_base + 2; - for (i = 0; i < j; i++) { - m->apicid_8132a[i][0] = apicid_base + 3 + i * 2; - m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1; - } - -} diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c deleted file mode 100644 index 33d4837a5d..0000000000 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ /dev/null @@ -1,148 +0,0 @@ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdk8_sysconf.h> - -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - - uint8_t sum = 0; - int i; - - struct mb_sysconf_t *m; - - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_8111_0; - pirq->rtr_devfn = ((sysconf.sbdn + 1) << 3) | 0; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1022; - pirq->rtr_device = 0x746b; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - { - struct device *dev; - dev = - dev_find_slot(m->bus_8111_0, - PCI_DEVFN(sysconf.sbdn + 1, 3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ3 - PINTB = IRQ5 - PINTC = IRQ10 - PINTD = IRQ11 - */ - pci_write_config16(dev, 0x56, 0xba53); - } - } - -//pci bridge - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); - static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; - pci_assign_irqs(m->bus_8111_0, sysconf.sbdn + 1, slotIrqs_1_4); - write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - slot_num++; - - printk(BIOS_DEBUG, "setting Onboard AMD USB\n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11 }; - pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, m->bus_8111_1, 0, 0, 0, 0, 0, 0, 0, 0x4, - 0xdef8, 0, 0); - pirq_info++; - slot_num++; - -//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; - - int j = 0; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - j++; - - } - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c deleted file mode 100644 index 905a0d5f8f..0000000000 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <arch/acpi.h> -#include <cpu/amd/powernow.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <cpu/amd/amdk8_sysconf.h> -#include "mainboard.h" - -static void mainboard_enable(struct device *dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.h b/src/mainboard/iwill/dk8_htx/mainboard.h deleted file mode 100644 index 111b4457ca..0000000000 --- a/src/mainboard/iwill/dk8_htx/mainboard.h +++ /dev/null @@ -1 +0,0 @@ -unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h deleted file mode 100644 index 4933d480ed..0000000000 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_8132_0; - unsigned char bus_8132_1; - unsigned char bus_8132_2; - unsigned char bus_8111_0; - unsigned char bus_8111_1; - - unsigned char bus_8132a[7][3]; - - unsigned char bus_8151[7][2]; - - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; - - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; - -}; - -#endif diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c deleted file mode 100644 index daf9b421f0..0000000000 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ /dev/null @@ -1,186 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) -#include <cpu/amd/multicore.h> -#endif -#include <cpu/amd/amdk8_sysconf.h> -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int i, j, bus_isa; - struct mb_sysconf_t *m; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 - { - struct device *dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132_1, 0x11, - res2mmio(res, 0, 0)); - } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132_2, 0x11, - res2mmio(res, 0, 0)); - } - } - - j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - switch(sysconf.hcid[i]) { - case 1: // 8132 - case 3: // 8131 - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, - res2mmio(res, 0, 0)); - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, - res2mmio(res, 0, 0)); - } - } - break; - } - j++; - } - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); - -//??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); - -// Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13); - -// Onboard VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12); - -//Slot 5 PCI 32 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 - } - -//Slot 6 PCI 32 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 - } -//Slot 1: HTX - -//Slot 2 PCI-X 133/100/66 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30 - } - -//Slot 3 PCI-X 133/100/66 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25 - } - -//Slot 4 PCI-X 133/100/66 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26 - } - -//Onboard NICS - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24 - -//Onboard SATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25 - - j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - int ii; - struct device *dev; - struct resource *res; - switch(sysconf.hcid[i]) { - case 1: - case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 1 PCI-X 133/100/66 - for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // - } - } - } - - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 2 PCI-X 133/100/66 - for(ii = 0; ii < 4; ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 - } - } - } - - break; - case 2: - - // Slot AGP - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); - break; - } - - j++; - } - - - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c deleted file mode 100644 index 11e80eadce..0000000000 --- a/src/mainboard/iwill/dk8_htx/resourcemap.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * - */ - -static void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c deleted file mode 100644 index f573cf58f9..0000000000 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ /dev/null @@ -1,163 +0,0 @@ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/amd/model_fxx_rev.h> -#include "southbridge/amd/amd8111/early_smbus.c" -#include <northbridge/amd/amdk8/raminit.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <delay.h> - -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include <northbridge/amd/amdk8/pre_f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -unsigned get_sbdn(unsigned bus); - -/* - * GPIO28 of 8111 will control H0_MEMRESET_L - * GPIO29 of 8111 will control H1_MEMRESET_L - */ -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low. */ - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines. */ - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } else { - /* Ensure the CPU has control of the memory lines. */ - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } -} - -void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset_high */ - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); - } -} - -void activate_spd_rom(const struct mem_controller *ctrl) { } - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "southbridge/amd/amd8111/early_ctrl.c" -#include <northbridge/amd/amdk8/amdk8.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" -#include <spd.h> -#include "cpu/amd/model_fxx/init_cpus.c" -#include "cpu/amd/model_fxx/fidvid.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, - }; - - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - - setup_mb_resource_map(); - - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - - setup_coherent_ht_domain(); // routing table and start other core0 - - wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if IS_ENABLED(CONFIG_SET_FIDVID) - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } -#endif - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } - - allow_all_aps_stop(bsp_apicid); - - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - enable_smbus(); - -#if 0 - dump_smbus_registers(); -#endif - - memreset_setup(); - - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synchronize FID/VID - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - -#if 0 - dump_pci_devices(); -#endif -} diff --git a/src/mainboard/iwill/dk8_htx/ssdt2.asl b/src/mainboard/iwill/dk8_htx/ssdt2.asl deleted file mode 100644 index a86594bf9f..0000000000 --- a/src/mainboard/iwill/dk8_htx/ssdt2.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2005 AMD - */ -DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci2_hc.asl" - } - } - -} diff --git a/src/mainboard/iwill/dk8_htx/ssdt3.asl b/src/mainboard/iwill/dk8_htx/ssdt3.asl deleted file mode 100644 index e4f299096f..0000000000 --- a/src/mainboard/iwill/dk8_htx/ssdt3.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2005 AMD - */ -DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci3_hc.asl" - } - } - -} diff --git a/src/mainboard/iwill/dk8_htx/ssdt4.asl b/src/mainboard/iwill/dk8_htx/ssdt4.asl deleted file mode 100644 index 71a02efd8a..0000000000 --- a/src/mainboard/iwill/dk8_htx/ssdt4.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2005 AMD - */ -DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci4_hc.asl" - } - } - -} diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl deleted file mode 100644 index 37886a9f99..0000000000 --- a/src/mainboard/iwill/dk8_htx/ssdt5.asl +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2005 AMD - */ -DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci5_hc.asl" - } - } - -} |