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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/iwill/dk8x
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwill/dk8x')
-rw-r--r--src/mainboard/iwill/dk8x/devicetree.cb16
-rw-r--r--src/mainboard/iwill/dk8x/irq_tables.c6
-rw-r--r--src/mainboard/iwill/dk8x/romstage.c12
3 files changed, 17 insertions, 17 deletions
diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb
index 77c96aa944..a275425751 100644
--- a/src/mainboard/iwill/dk8x/devicetree.cb
+++ b/src/mainboard/iwill/dk8x/devicetree.cb
@@ -1,8 +1,8 @@
chip northbridge/amd/amdk8/root_complex
device pci_domain 0 on
chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
device pci 0.0 on end
@@ -28,15 +28,15 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.4 on end
device pnp 2e.5 on end
device pnp 2e.6 on end
- device pnp 2e.7 on end
- device pnp 2e.8 on end
- device pnp 2e.9 on end
- device pnp 2e.a on end
+ device pnp 2e.7 on end
+ device pnp 2e.8 on end
+ device pnp 2e.9 on end
+ device pnp 2e.a on end
end
end
device pci 1.1 on end
device pci 1.2 on end
- device pci 1.3 on end
+ device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
end
@@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.2 on end
device pci 19.3 on end
end
- end
+ end
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c
index 1f35cbaef2..06b9cfb6b5 100644
--- a/src/mainboard/iwill/dk8x/irq_tables.c
+++ b/src/mainboard/iwill/dk8x/irq_tables.c
@@ -12,13 +12,13 @@
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
/* Each IRQ_SLOT entry consists of:
- * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
+ * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
*/
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT
* devices on the bus */
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
@@ -28,7 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = {
0x00, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x00, /* u8 checksum , mod 256 checksum must give
- * zero, will be corrected later
+ * zero, will be corrected later
*/
{
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 8dc9dc0049..9a2fede061 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -1,7 +1,7 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-#define SET_NB_CFG_54 1
+#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
@@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
+ * (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
-
+
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
@@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif