diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-08 15:46:37 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-08 15:46:37 +0000 |
commit | af97d33ec426b9414133fd82d958cf9ab52a390f (patch) | |
tree | d99f6480914df848dabb0ec197864e0c8f64d939 /src/mainboard/iwill/dk8_htx/ssdt5.asl | |
parent | 0e92974904703272b55d66dc4959d95adba6f30c (diff) |
Clean up ACPI:
- unify all iasl related rules into the toplevel Makefile
- build a filesystem standard for ACPI files and use it
- pass ACPI sources through cpp, so constants can be shared
between C and ACPI more easily
- use cpp's #include instead of ACPI's Include() so cpp gets
the whole picture
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwill/dk8_htx/ssdt5.asl')
-rw-r--r-- | src/mainboard/iwill/dk8_htx/ssdt5.asl | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl new file mode 100644 index 0000000000..7592301902 --- /dev/null +++ b/src/mainboard/iwill/dk8_htx/ssdt5.asl @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + #include "acpi/pci5_hc.asl" + } + } + +} + |