Fix a few whitespace and coding style issues.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 233 insertions, 218 deletions

diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
index 37b0a0b3a7..92874bc76d 100644
--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
+++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
@@ -35,18 +35,19 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/nvs.h" // FIXME: our own copy of nvs would be nice
-static void acpi_create_gnvs(global_nvs_t *gnvs)
+#include "southbridge/intel/i82801gx/nvs.h"	// FIXME: our own copy of nvs would be nice
+
+static void acpi_create_gnvs(global_nvs_t * gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));
 	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->mpen = 1;		/* Enable Multi Processing. */
 
-	/* Enable both COM ports */
+	/* Enable both COM ports. */
 	gnvs->cmap = 0x01;
 	gnvs->cmbp = 0x01;
 
-	/* IGD Displays */
+	/* IGD Displays. */
 	gnvs->ndid = 3;
 	gnvs->did[0] = 0x80000100;
 	gnvs->did[1] = 0x80000240;
@@ -55,15 +56,15 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->did[4] = 0x00000005;
 }
 
-static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+static void acpi_create_intel_hpet(acpi_hpet_t *hpet)
 {
 #define HPET_ADDR  0xfed00000ULL
 	acpi_header_t *header = &(hpet->header);
 	acpi_addr_t *addr = &(hpet->addr);
 
-	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+	memset((void *)hpet, 0, sizeof(acpi_hpet_t));
 
-	/* fill out header fields */
+	/* Fill out header fields. */
 	memcpy(header->signature, "HPET", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
@@ -72,7 +73,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	header->length = sizeof(acpi_hpet_t);
 	header->revision = 1;
 
-	/* fill out HPET address */
+	/* Fill out HPET address. */
 	addr->space_id = 0;	/* Memory */
 	addr->bit_width = 64;
 	addr->bit_offset = 0;
@@ -83,8 +84,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 	hpet->number = 0x00;
 	hpet->min_tick = 0x0080;
 
-	header->checksum =
-	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+	header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
@@ -94,26 +94,29 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	/* IOAPIC */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
+					   2, IO_APIC_ADDR, 0);
 
 	/* INT_SRC_OVR */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
+						current, 0, 0, 2, 0);
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+						current, 0, 9, 9,
+						MP_IRQ_TRIGGER_LEVEL |
+						MP_IRQ_POLARITY_HIGH);
 
 	return current;
 }
 
-unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+				       const char *oem_table_id)
 {
 	generate_cpu_entries();
-	return (unsigned long) (acpigen_get_current());
+	return (unsigned long)(acpigen_get_current());
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-	// Not implemented
+	/* Not implemented. */
 	return current;
 }
 
@@ -130,6 +133,7 @@ unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
 	int i;
+
 	acpi_rsdp_t *rsdp;
 	acpi_rsdt_t *rsdt;
 	acpi_xsdt_t *xsdt;
@@ -163,7 +167,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	ALIGN_CURRENT;
 
 	/* clear all table memory */
-	memset((void *) start, 0, current - start);
+	memset((void *)start, 0, current - start);
 
 	acpi_write_rsdp(rsdp, rsdt, xsdt);
 	acpi_write_rsdt(rsdt);
@@ -210,16 +214,18 @@ unsigned long write_acpi_tables(unsigned long start)
 	ALIGN_CURRENT;
 
 	/* Pack GNVS into the ACPI table area */
-	for (i=0; i < dsdt->length; i++) {
-		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
-			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+	for (i = 0; i < dsdt->length; i++) {
+		if (*(u32 *) (((u32) dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			       "DSDT at offset 0x%04x -> 0x%08lx\n",
+			       i, current);
+			*(u32 *) (((u32) dsdt) + i) = current;	// 0x92 bytes
 			break;
 		}
 	}
 
 	/* And fill it */
-	acpi_create_gnvs((global_nvs_t *)current);
+	acpi_create_gnvs((global_nvs_t *) current);
 
 	current += 0x100;
 	ALIGN_CURRENT;
@@ -232,11 +238,11 @@ unsigned long write_acpi_tables(unsigned long start)
 	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
 
 	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
+	       dsdt->length);
 
 #if CONFIG_HAVE_ACPI_SLIC
 	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
+	slic = (acpi_header_t *) current;
 	current += acpi_create_slic(current);
 	ALIGN_CURRENT;
 	acpi_add_table(rsdp, slic);
@@ -251,7 +257,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_add_table(rsdp, fadt);
 
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
+	ssdt = (acpi_header_t *) current;
 	acpi_create_ssdt_generator(ssdt, "COREBOOT");
 	current += ssdt->length;
 	acpi_add_table(rsdp, ssdt);
diff --git a/src/mainboard/iwave/iWRainbowG6/dmi.h b/src/mainboard/iwave/iWRainbowG6/dmi.h
index cb48d72a1c..d076dff914 100644
--- a/src/mainboard/iwave/iWRainbowG6/dmi.h
+++ b/src/mainboard/iwave/iWRainbowG6/dmi.h
@@ -20,10 +20,15 @@
 #define DMI_TABLE_SIZE 0x55
 
 static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00,
+	    0x00, 0x00, 0x00, 0x00,
+	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00,
+	    0x01, 0x00, 0x23, 0x00,
+	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde,
+	    0xcb, 0x7f, 0x00, 0x00,
+	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74,
+	    0x65, 0x6d, 0x73, 0x20,
+	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f,
+	    0x31, 0x33, 0x2f, 0x32,
 	0x30, 0x30, 0x38, 0x00, 0x00
 };
diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c
index a0e381fb13..ae58bbfa6b 100644
--- a/src/mainboard/iwave/iWRainbowG6/fadt.c
+++ b/src/mainboard/iwave/iWRainbowG6/fadt.c
@@ -35,28 +35,29 @@
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+				       0x40) & 0xfffe;
 
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
- 	header->length = sizeof(acpi_fadt_t);
- 	header->revision = 3;
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
 	memcpy(header->oem_id, "CORE  ", 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, "CORE", 4);
 	header->asl_compiler_revision = 1;
 
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
+	fadt->firmware_ctrl = (unsigned long)facs;
+	fadt->dsdt = (unsigned long)dsdt;
 	fadt->model = 1;
 	fadt->preferred_pm_profile = PM_MOBILE;
 
-  	fadt->sci_int = 0x9;
- 	fadt->smi_cmd = APM_CNT;
- 	fadt->acpi_enable = ACPI_ENABLE;
- 	fadt->acpi_disable = ACPI_DISABLE;
-  	fadt->s4bios_req = 0x0;
- 	fadt->pstate_cnt = PST_CONTROL;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = PST_CONTROL;
 
 	fadt->pm1a_evt_blk = pmbase;
 	fadt->pm1b_evt_blk = 0x0;
@@ -75,7 +76,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->gpe0_blk_len = 8;
 	fadt->gpe1_blk_len = 0;
 	fadt->gpe1_base = 0;
- 	fadt->cst_cnt = CST_CONTROL;
+	fadt->cst_cnt = CST_CONTROL;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
 	fadt->flush_size = 1024;
@@ -87,79 +88,78 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->century = 0x00;
 	fadt->iapc_boot_arch = 0x03;
 
- 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- 	fadt->reset_reg.space_id = 0;
- 	fadt->reset_reg.bit_width = 0;
- 	fadt->reset_reg.bit_offset = 0;
- 	fadt->reset_reg.resv = 0;
- 	fadt->reset_reg.addrl = 0x0;
- 	fadt->reset_reg.addrh = 0x0;
-
- 	fadt->reset_value = 0;
- 	fadt->x_firmware_ctl_l = (unsigned long)facs;
- 	fadt->x_firmware_ctl_h = 0;
- 	fadt->x_dsdt_l = (unsigned long)dsdt;
- 	fadt->x_dsdt_h = 0;
-
- 	fadt->x_pm1a_evt_blk.space_id = 1;
- 	fadt->x_pm1a_evt_blk.bit_width = 32;
- 	fadt->x_pm1a_evt_blk.bit_offset = 0;
- 	fadt->x_pm1a_evt_blk.resv = 0;
- 	fadt->x_pm1a_evt_blk.addrl = pmbase;
- 	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_evt_blk.space_id = 1;
- 	fadt->x_pm1b_evt_blk.bit_width = 0;
- 	fadt->x_pm1b_evt_blk.bit_offset = 0;
- 	fadt->x_pm1b_evt_blk.resv = 0;
- 	fadt->x_pm1b_evt_blk.addrl = 0x0;
- 	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- 	fadt->x_pm1a_cnt_blk.space_id = 1;
- 	fadt->x_pm1a_cnt_blk.bit_width = 16;
- 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1a_cnt_blk.resv = 0;
- 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm1b_cnt_blk.space_id = 1;
- 	fadt->x_pm1b_cnt_blk.bit_width = 0;
- 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
- 	fadt->x_pm1b_cnt_blk.resv = 0;
- 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
- 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm2_cnt_blk.space_id = 1;
- 	fadt->x_pm2_cnt_blk.bit_width = 8;
- 	fadt->x_pm2_cnt_blk.bit_offset = 0;
- 	fadt->x_pm2_cnt_blk.resv = 0;
- 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- 	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- 	fadt->x_pm_tmr_blk.space_id = 1;
- 	fadt->x_pm_tmr_blk.bit_width = 32;
- 	fadt->x_pm_tmr_blk.bit_offset = 0;
- 	fadt->x_pm_tmr_blk.resv = 0;
- 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
- 	fadt->x_gpe0_blk.space_id = 1;
- 	fadt->x_gpe0_blk.bit_width = 64;
- 	fadt->x_gpe0_blk.bit_offset = 0;
- 	fadt->x_gpe0_blk.resv = 0;
- 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- 	fadt->x_gpe0_blk.addrh = 0x0;
-
- 	fadt->x_gpe1_blk.space_id = 1;
- 	fadt->x_gpe1_blk.bit_width = 0;
- 	fadt->x_gpe1_blk.bit_offset = 0;
- 	fadt->x_gpe1_blk.resv = 0;
- 	fadt->x_gpe1_blk.addrl = 0x0;
- 	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+	    ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+	    ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, header->length);
 }
diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.h b/src/mainboard/iwave/iWRainbowG6/hda_verb.h
index 0542b4e76e..80ed21d522 100644
--- a/src/mainboard/iwave/iWRainbowG6/hda_verb.h
+++ b/src/mainboard/iwave/iWRainbowG6/hda_verb.h
@@ -18,76 +18,77 @@
  */
 
 static u32 mainboard_cim_verb_data[] = {
-        /* coreboot specific header */
-        0x111d76d5,     // Codec Vendor / Device ID: IDT / 92HD81
-        0x00000000,     // Subsystem ID
-        0x0000000a,     // Number of jacks
+	/* coreboot specific header */
+	0x111d76d5,		// Codec Vendor / Device ID: IDT 92HD81
+	0x00000000,		// Subsystem ID
+	0x0000000a,		// Number of jacks
 
-	//Codec 92HD81 Yangtze 4ch Pin Port A, data = 0x02a11040
+	/* NID 0x0a, Port A (capless headphone) */
 	0x0A71C40,
 	0x0A71D10,
 	0x0A71EA1,
 	0x0A71F02,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Port B, data = 0x0221101f
+	/* NID 0x0b, Port B (capless headphone) */
 	0x0B71C1F,
 	0x0B71D10,
 	0x0B71E21,
 	0x0B71F02,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Port C, data = 0x400000f0
+	/*
+	 * NID 0x0c, Port C (Line IN/OUT+MIC for YD/UA revisions, and
+	 * Line IN+MIC for TA revision)
+	 */
 	0x0C71CF0,
 	0x0C71D00,
 	0x0C71E00,
 	0x0C71F40,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Port D, data = 0x10104110
+	/* NID 0x0d, Port D (BTL output - EAPD control) */
 	0x0D71C10,
 	0x0D71D41,
 	0x0D71E10,
 	0x0D71F10,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Port E, data = 0x400000f0
+	/* NID 0x0e, Port E (Line IN/OUT) */
 	0x0E71CF0,
 	0x0E71D00,
 	0x0E71E00,
 	0x0E71F40,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Port F, data = 0x400000f0
+	/* NID 0x0f, Port F (Line IN/OUT, MIC) */
 	0x0F71CF0,
 	0x0F71D00,
 	0x0F71E00,
 	0x0F71F40,
 
-	//;Codec 92HD81 Yangtze 4ch Pin MonoOut, data = 0x40f000f0
+	/* NID 0x10, MonoOut (output-only) */
 	0x1071CF0,
 	0x1071D00,
 	0x1071EF0,
 	0x1071F40,
 
-	//;Codec 92HD81 Yangtze 4ch Pin DMic0, data = 0x400000f0
+	/* NID 0x10, DigMic0 (Digital Microphone 0) */
 	0x1171CF0,
 	0x1171D00,
 	0x1171E00,
 	0x1171F40,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Dig0Pin, data = 0x10402150
+	/* NID 0x1f, Dig0Pin (First Digital Output Pin) */
 	0x1F71C50,
 	0x1F71D21,
 	0x1F71E40,
 	0x1F71F10,
 
-	//;Codec 92HD81 Yangtze 4ch Pin Dig1Pin, data = 0x400000f0
+	/* NID 0x20, Dig1Pin (Second Digital Output Pin / DMIC Input Pin) */
 	0x2071CF0,
 	0x2071D00,
 	0x2071E00,
 	0x2071F40,
 
-	//; BTL Gain
-	0x017F417
-	// ; Gain = 16.79dB
+	/* BTL Gain */
+	0x017F417, /* Gain = 16.79dB */
 };
 
 extern const u32 *cim_verb_data;
 extern u32 cim_verb_data_size;
-
diff --git a/src/mainboard/iwave/iWRainbowG6/irq_tables.c b/src/mainboard/iwave/iWRainbowG6/irq_tables.c
index 12daec911a..3f11f16ffd 100644
--- a/src/mainboard/iwave/iWRainbowG6/irq_tables.c
+++ b/src/mainboard/iwave/iWRainbowG6/irq_tables.c
@@ -20,37 +20,36 @@
 #include <arch/pirq_routing.h>
 
 const struct irq_routing_table intel_irq_routing_table = {
-        PIRQ_SIGNATURE,         /* u32 signature */
-        PIRQ_VERSION,           /* u16 version */
-        32+16*CONFIG_IRQ_SLOT_COUNT,     /* Max. number of devices on the bus */
-        0x00,                   /* Interrupt router bus */
-        (0x1f << 3) | 0x0,      /* Interrupt router dev */
-        0,                      /* IRQs devoted exclusively to PCI usage */
-        0x8086,                 /* Vendor */
-        0x8119,                 /* Device*/
+	PIRQ_SIGNATURE,         /* u32 signature */
+	PIRQ_VERSION,           /* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
+	0x00,                   /* Interrupt router bus */
+	(0x1f << 3) | 0x0,      /* Interrupt router dev */
+	0,                      /* IRQs devoted exclusively to PCI usage */
+	0x8086,                 /* Vendor */
+	0x8119,                 /* Device*/
 	0,                      /* Miniport */
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-        0xdf,                   /* Checksum (has to be set to some value that
-                                 * would give 0 after the sum of all bytes
-                                 * for this structure (including checksum).
-                                 */
-        {
-                /* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-                {0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},
-                {0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-                {0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},
-                {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-        }
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xdf,                   /* Checksum (has to be set to some value that
+	                         * would give 0 after the sum of all bytes
+	                         * for this structure (including checksum).
+	                         */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},
+		{0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},
+		{0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+	}
 };
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-        return copy_pirq_routing_table(addr);
+	return copy_pirq_routing_table(addr);
 }
-
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c
index 2096be2f0a..7d0c61d7cd 100644
--- a/src/mainboard/iwave/iWRainbowG6/mainboard.c
+++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c
@@ -39,4 +39,3 @@ struct chip_operations mainboard_ops = {
 	CHIP_NAME("iW Rainbow G6 Mainboard")
 	.enable_dev = mainboard_enable,
 };
-
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c b/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c
index 020e2c3cba..fc4defb096 100644
--- a/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c
+++ b/src/mainboard/iwave/iWRainbowG6/mainboard_smi.c
@@ -23,30 +23,30 @@
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs
 
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
+/*
+ * The southbridge SMI handler checks whether gnvs has a valid pointer before
+ * calling the trap handler.
  */
-//extern global_nvs_t *gnvs;
+// extern global_nvs_t *gnvs;
 
 int mainboard_io_trap_handler(int smif)
 {
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		//gnvs->smif = 0;
+		// gnvs->smif = 0;
 		break;
 	default:
 		return 0;
 	}
 
-	/* On success, the IO Trap Handler returns 0
-	 * On failure, the IO Trap Handler returns a value != 0
+	/*
+	 * On success, the IO Trap Handler returns 0.
+	 * On failure, the IO Trap Handler returns a value != 0.
 	 *
 	 * For now, we force the return value to 0 and log all traps to
 	 * see what's going on.
 	 */
-	//gnvs->smif = 0;
+	// gnvs->smif = 0;
 	return 1;
 }
-
-
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
index 339a8f5eec..05a0d9f10b 100644
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ b/src/mainboard/iwave/iWRainbowG6/romstage.c
@@ -5,8 +5,7 @@
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,13 +14,11 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include <stdint.h>
 #include <string.h>
-
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
@@ -29,16 +26,12 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
 #include <arch/cpu.h>
-
 #include <console/console.h>
 #if 0
 #include "ram/ramtest.c"
 #include "southbridge/intel/sch/early_smbus.c"
 #endif
 
-//#include "pc80/mc146818rtc_early.c"
-//#include "pc80/serial.c"
-
 #define RFID_TEST 0
 
 #if RFID_TEST
@@ -51,15 +44,18 @@
 static u32 sch_SMbase_read(void)
 {
 	u32 SMBusBase;
-	SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40);	/*SM Bus Address */
+
+	/* SMBus address */
+	SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40);
 	SMBusBase &= 0xFFFF;
-	printk(BIOS_DEBUG, "SM Bus Base. =%x\r\n", SMBusBase);
+	printk(BIOS_DEBUG, "SMBus base = %x\r\n", SMBusBase);
 	return SMBusBase;
 }
 
 static void sch_SMbase_init(void)
 {
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	outb(0x3F, SMBusBase + SMBCLKDIV);
 }
@@ -67,6 +63,7 @@ static void sch_SMbase_init(void)
 static void sch_SMbus_regs(void)
 {
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	printk(BIOS_DEBUG, "SMBHSTCNT. =%x\r\n", inb(SMBusBase + SMBHSTCNT));
 	printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", inb(SMBusBase + SMBHSTSTS));
@@ -76,17 +73,19 @@ static void sch_SMbus_regs(void)
 	printk(BIOS_DEBUG, "SMBHSTCMD. =%x\r\n", inb(SMBusBase + SMBHSTCMD));
 }
 
-void smb_clear()
+void smb_clear(void)
 {
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	outb(0x00, SMBusBase + SMBHSTCNT);
 	outb(0x07, SMBusBase + SMBHSTSTS);
 }
 
-void data_clear()
+void data_clear(void)
 {
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	outb(0x00, SMBusBase + SMBHSTDAT0);
 	outb(0x00, SMBusBase + SMBHSTCMD);
@@ -104,6 +103,7 @@ void transaction1(unsigned char dev_addr)
 {
 	int temp, a;
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	printk(BIOS_DEBUG, "Transaction 1");
 	//clear the control and status registers
@@ -127,36 +127,37 @@ void transaction1(unsigned char dev_addr)
 	//check the status register for busy state
 	//sch_SMbus_regs ();
 	temp = inb(SMBusBase + SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
 	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
 	do {
 		temp = inb(SMBusBase + SMBHSTSTS);
-		printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp);
+		printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
 		//sch_SMbus_regs ();
 		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-			     inb(SMBusBase + SMBHSTSTS));
+		       inb(SMBusBase + SMBHSTSTS));
 		if (temp > 0)
 			break;
 	} while (1);
 
 	switch (temp) {
 	case 1:
-		printk(BIOS_DEBUG, "SM Bus Success");
+		printk(BIOS_DEBUG, "SMBus Success");
 		break;
 	default:
-		printk(BIOS_DEBUG, "SM Bus error %d", temp);
+		printk(BIOS_DEBUG, "SMBus error %d", temp);
 		break;
 
 	}
 	sch_SMbus_regs();
 	printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n",
-		     inb(SMBusBase + SMBHSTCMD));
+	       inb(SMBusBase + SMBHSTCMD));
 }
 
 void transaction2(unsigned char dev_addr)
 {
 	int temp, a;
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	printk(BIOS_DEBUG, "Transaction 2");
 	//clear the control and status registers
@@ -175,37 +176,38 @@ void transaction2(unsigned char dev_addr)
 	//check the status register for busy state
 	//sch_SMbus_regs ();
 	temp = inb(SMBusBase + SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
 	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
 	do {
 		temp = inb(SMBusBase + SMBHSTSTS);
-		printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp);
+		printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
 		//sch_SMbus_regs ();
 		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-			     inb(SMBusBase + SMBHSTSTS));
+		       inb(SMBusBase + SMBHSTSTS));
 		if (temp > 0)
 			break;
 	} while (1);
 
 	switch (temp) {
 	case 1:
-		printk(BIOS_DEBUG, "SM Bus Success");
+		printk(BIOS_DEBUG, "SMBus Success");
 		break;
 	default:
-		printk(BIOS_DEBUG, "SM Bus error %d", temp);
+		printk(BIOS_DEBUG, "SMBus error %d", temp);
 		break;
 
 	}
 	sch_SMbus_regs();
 
 	printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n",
-		     inb(SMBusBase + SMBHSTCMD));
+	       inb(SMBusBase + SMBHSTCMD));
 }
 
 void transaction3(unsigned char dev_addr)
 {
 	int temp, index, length;
 	u32 SMBusBase;
+
 	SMBusBase = sch_SMbase_read();
 	printk(BIOS_DEBUG, "smb_read_multiple_bytes");
 	smb_clear();
@@ -222,13 +224,13 @@ void transaction3(unsigned char dev_addr)
 	// sch_SMbus_regs ();
 	//check the status register for busy state
 	//temp=inb(SMBusBase+SMBHSTSTS);
-	//printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+	//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
 	//sch_SMbus_regs ();
 	//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
 	do {
 		temp = inb(SMBusBase + SMBHSTSTS);
 		printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
-			     inb(SMBusBase + SMBHSTSTS));
+		       inb(SMBusBase + SMBHSTSTS));
 		//sch_SMbus_regs ();
 		if (temp > 0)
 			break;
@@ -236,10 +238,10 @@ void transaction3(unsigned char dev_addr)
 
 	switch (temp) {
 	case 1:
-		printk(BIOS_DEBUG, "SM Bus Success\n");
+		printk(BIOS_DEBUG, "SMBus Success\n");
 		break;
 	default:
-		printk(BIOS_DEBUG, "SM Bus error %d", temp);
+		printk(BIOS_DEBUG, "SMBus error %d", temp);
 		break;
 
 	}
@@ -254,12 +256,13 @@ void transaction3(unsigned char dev_addr)
 	printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1));
 	for (index = 0; index < length; index++)
 		printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index,
-			     inb(SMBusBase + SMBHSTDATB + index));
+		       inb(SMBusBase + SMBHSTDATB + index));
 }
 
 int selectcard(void)
 {
 	int i;
+
 	printk(BIOS_DEBUG, "%s", "\r\nCase 9....... \n\r");
 	// send the length byte and command code through RFID interface
 
@@ -274,7 +277,6 @@ int selectcard(void)
 #include "northbridge/intel/sch/raminit.h"
 #include "northbridge/intel/sch/raminit.c"
 
-
 static void sch_enable_lpc(void)
 {
 	/* Initialize the FWH decode/Enable registers according to platform design */
@@ -287,6 +289,7 @@ static void sch_enable_lpc(void)
 static void sch_shadow_CMC(void)
 {
 	u32 reg32;
+
 	/* FIXME: proper dest, proper src, and wbinvd, too */
 	memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024);
 	// __asm__ volatile ("wbinvd \n"
@@ -299,7 +302,8 @@ static void sch_shadow_CMC(void)
 
 	reg32 = cpuid_eax(0x80000008);
 	printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF));
-	printk(BIOS_INFO, "Virtual Address size: %d.\n", ((reg32 & 0xFF00) >> 8));
+	printk(BIOS_INFO, "Virtual Address size: %d.\n",
+	       ((reg32 & 0xFF00) >> 8));
 	sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000);
 	printk(BIOS_DEBUG, "1 ");
 	sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32);
@@ -318,10 +322,11 @@ static void poulsbo_setup_Stage1Regs(void)
 static void poulsbo_setup_Stage2Regs(void)
 {
 	u32 reg32;
+
 	printk(BIOS_DEBUG, "Reserved");
 	reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62);
 	pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3));
-	/*Slot capabilities */
+	/* Slot capabilities */
 	pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
 	pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);
 	/* FIXME: CPU ID identification */
@@ -332,21 +337,20 @@ void main(unsigned long bist)
 {
 	int boot_mode = 0;
 
-	if (bist == 0) {
+	if (bist == 0)
 		enable_lapic();
-	}
 
 	sch_enable_lpc();
-	/* Set up the console */
 	uart_init();
 	console_init();
 
 	/* Halt if there was a built in self test failure */
 	// report_bist_failure(bist);
-	// outl (0x00,0x1088);
+	// outl (0x00, 0x1088);
 
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
+	/*
+	 * Perform some early chipset initialization required
+	 * before RAM initialization can work.
 	 */
 	sch_early_initialization();
 	sdram_initialize(boot_mode);
@@ -355,13 +359,14 @@ void main(unsigned long bist)
 	poulsbo_setup_Stage1Regs();
 	poulsbo_setup_Stage2Regs();
 #if 0
-	sch_SMbase_init ();
+	sch_SMbase_init();
 
-	/* Perform some initialization that must run before stage2 */
+	/* Perform some initialization that must run before stage2. */
 #endif
 
-	/* This should probably go away. Until now it is required
-	 * and mainboard specific
+	/*
+	 * This should probably go away. Until now it is required
+	 * and mainboard specific.
 	 */
 
 	/* Chipset Errata! */