diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:43:48 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:43:20 +0200 |
| commit | 408d3928236f275633f8656cc12e32949d304d9f (patch) | |
| tree | a02149efa1a0b57c0ed8b5afe4bb76f98d35bff2 /src/mainboard/iwave | |
| parent | 07921540dda79d810d8bfc6be211513c238a0d63 (diff) | |
intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/iwave')
| -rw-r--r-- | src/mainboard/iwave/iWRainbowG6/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 37b442c0be..a6c5a715c3 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -20,6 +20,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> +#include <cpu/intel/romstage.h> #include <arch/cpu.h> #include <console/console.h> #if 0 @@ -328,8 +329,7 @@ static void poulsbo_setup_Stage2Regs(void) printk(BIOS_DEBUG, " done.\n"); } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int boot_mode = 0; |