diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-18 13:22:37 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-18 13:22:37 +0000 |
commit | 405721d45c8f7cd58c2466e43df8c2aee6f8e714 (patch) | |
tree | d9c981c99cf28f931032dabb26094494622f7bb6 /src/mainboard/iwave/iWRainbowG6/romstage.c | |
parent | a0360af0f1645d91b139022353f7a3a9f7f85f8a (diff) |
Fix a few whitespace and coding style issues.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwave/iWRainbowG6/romstage.c')
-rw-r--r-- | src/mainboard/iwave/iWRainbowG6/romstage.c | 91 |
1 files changed, 48 insertions, 43 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 339a8f5eec..05a0d9f10b 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,13 +14,11 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <stdint.h> #include <string.h> - #include <arch/io.h> #include <arch/romcc_io.h> #include <device/pci_def.h> @@ -29,16 +26,12 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <arch/cpu.h> - #include <console/console.h> #if 0 #include "ram/ramtest.c" #include "southbridge/intel/sch/early_smbus.c" #endif -//#include "pc80/mc146818rtc_early.c" -//#include "pc80/serial.c" - #define RFID_TEST 0 #if RFID_TEST @@ -51,15 +44,18 @@ static u32 sch_SMbase_read(void) { u32 SMBusBase; - SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40); /*SM Bus Address */ + + /* SMBus address */ + SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40); SMBusBase &= 0xFFFF; - printk(BIOS_DEBUG, "SM Bus Base. =%x\r\n", SMBusBase); + printk(BIOS_DEBUG, "SMBus base = %x\r\n", SMBusBase); return SMBusBase; } static void sch_SMbase_init(void) { u32 SMBusBase; + SMBusBase = sch_SMbase_read(); outb(0x3F, SMBusBase + SMBCLKDIV); } @@ -67,6 +63,7 @@ static void sch_SMbase_init(void) static void sch_SMbus_regs(void) { u32 SMBusBase; + SMBusBase = sch_SMbase_read(); printk(BIOS_DEBUG, "SMBHSTCNT. =%x\r\n", inb(SMBusBase + SMBHSTCNT)); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", inb(SMBusBase + SMBHSTSTS)); @@ -76,17 +73,19 @@ static void sch_SMbus_regs(void) printk(BIOS_DEBUG, "SMBHSTCMD. =%x\r\n", inb(SMBusBase + SMBHSTCMD)); } -void smb_clear() +void smb_clear(void) { u32 SMBusBase; + SMBusBase = sch_SMbase_read(); outb(0x00, SMBusBase + SMBHSTCNT); outb(0x07, SMBusBase + SMBHSTSTS); } -void data_clear() +void data_clear(void) { u32 SMBusBase; + SMBusBase = sch_SMbase_read(); outb(0x00, SMBusBase + SMBHSTDAT0); outb(0x00, SMBusBase + SMBHSTCMD); @@ -104,6 +103,7 @@ void transaction1(unsigned char dev_addr) { int temp, a; u32 SMBusBase; + SMBusBase = sch_SMbase_read(); printk(BIOS_DEBUG, "Transaction 1"); //clear the control and status registers @@ -127,36 +127,37 @@ void transaction1(unsigned char dev_addr) //check the status register for busy state //sch_SMbus_regs (); temp = inb(SMBusBase + SMBHSTSTS); - //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp); + //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); do { temp = inb(SMBusBase + SMBHSTSTS); - printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp); + printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp); //sch_SMbus_regs (); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); if (temp > 0) break; } while (1); switch (temp) { case 1: - printk(BIOS_DEBUG, "SM Bus Success"); + printk(BIOS_DEBUG, "SMBus Success"); break; default: - printk(BIOS_DEBUG, "SM Bus error %d", temp); + printk(BIOS_DEBUG, "SMBus error %d", temp); break; } sch_SMbus_regs(); printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n", - inb(SMBusBase + SMBHSTCMD)); + inb(SMBusBase + SMBHSTCMD)); } void transaction2(unsigned char dev_addr) { int temp, a; u32 SMBusBase; + SMBusBase = sch_SMbase_read(); printk(BIOS_DEBUG, "Transaction 2"); //clear the control and status registers @@ -175,37 +176,38 @@ void transaction2(unsigned char dev_addr) //check the status register for busy state //sch_SMbus_regs (); temp = inb(SMBusBase + SMBHSTSTS); - //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp); + //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); do { temp = inb(SMBusBase + SMBHSTSTS); - printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp); + printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp); //sch_SMbus_regs (); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); if (temp > 0) break; } while (1); switch (temp) { case 1: - printk(BIOS_DEBUG, "SM Bus Success"); + printk(BIOS_DEBUG, "SMBus Success"); break; default: - printk(BIOS_DEBUG, "SM Bus error %d", temp); + printk(BIOS_DEBUG, "SMBus error %d", temp); break; } sch_SMbus_regs(); printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n", - inb(SMBusBase + SMBHSTCMD)); + inb(SMBusBase + SMBHSTCMD)); } void transaction3(unsigned char dev_addr) { int temp, index, length; u32 SMBusBase; + SMBusBase = sch_SMbase_read(); printk(BIOS_DEBUG, "smb_read_multiple_bytes"); smb_clear(); @@ -222,13 +224,13 @@ void transaction3(unsigned char dev_addr) // sch_SMbus_regs (); //check the status register for busy state //temp=inb(SMBusBase+SMBHSTSTS); - //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp); + //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //sch_SMbus_regs (); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); do { temp = inb(SMBusBase + SMBHSTSTS); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); //sch_SMbus_regs (); if (temp > 0) break; @@ -236,10 +238,10 @@ void transaction3(unsigned char dev_addr) switch (temp) { case 1: - printk(BIOS_DEBUG, "SM Bus Success\n"); + printk(BIOS_DEBUG, "SMBus Success\n"); break; default: - printk(BIOS_DEBUG, "SM Bus error %d", temp); + printk(BIOS_DEBUG, "SMBus error %d", temp); break; } @@ -254,12 +256,13 @@ void transaction3(unsigned char dev_addr) printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1)); for (index = 0; index < length; index++) printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index, - inb(SMBusBase + SMBHSTDATB + index)); + inb(SMBusBase + SMBHSTDATB + index)); } int selectcard(void) { int i; + printk(BIOS_DEBUG, "%s", "\r\nCase 9....... \n\r"); // send the length byte and command code through RFID interface @@ -274,7 +277,6 @@ int selectcard(void) #include "northbridge/intel/sch/raminit.h" #include "northbridge/intel/sch/raminit.c" - static void sch_enable_lpc(void) { /* Initialize the FWH decode/Enable registers according to platform design */ @@ -287,6 +289,7 @@ static void sch_enable_lpc(void) static void sch_shadow_CMC(void) { u32 reg32; + /* FIXME: proper dest, proper src, and wbinvd, too */ memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024); // __asm__ volatile ("wbinvd \n" @@ -299,7 +302,8 @@ static void sch_shadow_CMC(void) reg32 = cpuid_eax(0x80000008); printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF)); - printk(BIOS_INFO, "Virtual Address size: %d.\n", ((reg32 & 0xFF00) >> 8)); + printk(BIOS_INFO, "Virtual Address size: %d.\n", + ((reg32 & 0xFF00) >> 8)); sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000); printk(BIOS_DEBUG, "1 "); sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32); @@ -318,10 +322,11 @@ static void poulsbo_setup_Stage1Regs(void) static void poulsbo_setup_Stage2Regs(void) { u32 reg32; + printk(BIOS_DEBUG, "Reserved"); reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62); pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); - /*Slot capabilities */ + /* Slot capabilities */ pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500); pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500); /* FIXME: CPU ID identification */ @@ -332,21 +337,20 @@ void main(unsigned long bist) { int boot_mode = 0; - if (bist == 0) { + if (bist == 0) enable_lapic(); - } sch_enable_lpc(); - /* Set up the console */ uart_init(); console_init(); /* Halt if there was a built in self test failure */ // report_bist_failure(bist); - // outl (0x00,0x1088); + // outl (0x00, 0x1088); - /* Perform some early chipset initialization required - * before RAM initialization can work + /* + * Perform some early chipset initialization required + * before RAM initialization can work. */ sch_early_initialization(); sdram_initialize(boot_mode); @@ -355,13 +359,14 @@ void main(unsigned long bist) poulsbo_setup_Stage1Regs(); poulsbo_setup_Stage2Regs(); #if 0 - sch_SMbase_init (); + sch_SMbase_init(); - /* Perform some initialization that must run before stage2 */ + /* Perform some initialization that must run before stage2. */ #endif - /* This should probably go away. Until now it is required - * and mainboard specific + /* + * This should probably go away. Until now it is required + * and mainboard specific. */ /* Chipset Errata! */ |