diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
commit | be61a173512ece32de01562995a91fbbf3f5b335 (patch) | |
tree | acf01fc4637bc97ca0e395158254a57ae247a402 /src/mainboard/iwave/iWRainbowG6/devicetree.cb | |
parent | 312fc96874ff2b3fd1a839b72dd10edb1b8937b8 (diff) |
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.
Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwave/iWRainbowG6/devicetree.cb')
-rw-r--r-- | src/mainboard/iwave/iWRainbowG6/devicetree.cb | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb new file mode 100644 index 0000000000..efae82b8ec --- /dev/null +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -0,0 +1,39 @@ +chip northbridge/intel/sch + + device lapic_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # Integrated Graphics and Video Device + + chip southbridge/intel/sch + register "pirqa_routing" = "0xa" + register "pirqb_routing" = "0xb" + register "pirqc_routing" = "0x5" + register "pirqd_routing" = "0xf" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + device pci 1a.0 on end # 26 0 USB Client + device pci 1b.0 on end # 27 0 HD Audio Controller + device pci 1c.0 on end # 28 0 PCI Express Port 1 + device pci 1c.1 on end # 28 1 PCI Express Port 2 + device pci 1d.0 on end # USB Classic UHCI Controller 1 + device pci 1d.1 on end # USB Classic UHCI Controller 2 + device pci 1d.2 on end # USB Classic UHCI Controller 3 + device pci 1d.7 on end # USB2 EHCI Controller + device pci 1e.0 on end # SDIO/MMC Port 0 + device pci 1e.1 on end # SDIO/MMC Port 1 + device pci 1e.2 on end # SDIO/MMC Port 2 + device pci 1f.0 on end # LPC bridge + device pci 1f.1 on end # PATA Controller + end + end +end + |