diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 14:20:28 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:23:30 +0000 |
commit | 0026a53562595cafb466e4ff836c50a7817d5297 (patch) | |
tree | 4d5f4062df24cdaa0109e9bddac81c587ea36d0e /src/mainboard/iwave/iWRainbowG6/devicetree.cb | |
parent | 732fb2ab5363968a12b2270319189c2a2a536a36 (diff) |
Intel sch board & chip: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/intel/sch
Mainboards:
mainboard/iwave/iWRainbowG6
Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/iwave/iWRainbowG6/devicetree.cb')
-rw-r--r-- | src/mainboard/iwave/iWRainbowG6/devicetree.cb | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb deleted file mode 100644 index b13d87300b..0000000000 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ /dev/null @@ -1,40 +0,0 @@ -chip soc/intel/sch - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # PIRQ routing - register "pirqa_routing" = "0xa" - register "pirqb_routing" = "0xb" - register "pirqc_routing" = "0x5" - register "pirqd_routing" = "0xf" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - device cpu_cluster 0 on - chip cpu/intel/socket_441 - device lapic 0 on end - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # Integrated Graphics and Video Device - - device pci 1a.0 on end # 26 0 USB Client - device pci 1b.0 on end # 27 0 HD Audio Controller - device pci 1c.0 on end # 28 0 PCI Express Port 1 - device pci 1c.1 on end # 28 1 PCI Express Port 2 - device pci 1d.0 on end # USB Classic UHCI Controller 1 - device pci 1d.1 on end # USB Classic UHCI Controller 2 - device pci 1d.2 on end # USB Classic UHCI Controller 3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on end # SDIO/MMC Port 0 - device pci 1e.1 on end # SDIO/MMC Port 1 - device pci 1e.2 on end # SDIO/MMC Port 2 - device pci 1f.0 on end # LPC bridge - device pci 1f.1 on end # PATA Controller - end -end |